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Message-ID: <CAEEQ3w=zAzwnbQaSC3JBMcGODt0xzud-fuYvVRA9=C-2tEX_Rg@mail.gmail.com>
Date: Tue, 29 Apr 2025 11:41:32 +0800
From: yunhui cui <cuiyunhui@...edance.com>
To: Jiri Slaby <jirislaby@...nel.org>
Cc: arnd@...db.de, andriy.shevchenko@...ux.intel.com, 
	benjamin.larsson@...exis.eu, gregkh@...uxfoundation.org, 
	heikki.krogerus@...ux.intel.com, ilpo.jarvinen@...ux.intel.com, 
	jkeeping@...usicbrands.com, john.ogness@...utronix.de, 
	linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org, 
	markus.mayer@...aro.org, matt.porter@...aro.org, namcao@...utronix.de, 
	paulmck@...nel.org, pmladek@...e.com, schnelle@...ux.ibm.com, 
	sunilvl@...tanamicro.com, tim.kryger@...aro.org
Subject: Re: [External] Re: [PATCH v4 4/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT

On Sun, Apr 27, 2025 at 7:17 PM yunhui cui <cuiyunhui@...edance.com> wrote:
>
> Hi js,
>
>
> On Fri, Apr 25, 2025 at 2:43 PM Jiri Slaby <jirislaby@...nel.org> wrote:
> >
> > On 25. 04. 25, 8:41, Jiri Slaby wrote:
> > > On 25. 04. 25, 8:24, Yunhui Cui wrote:
> > >> In the case of RX_TIMEOUT, to avoid PSLVERR, disable the FIFO
> > >> before reading UART_RX when UART_LSR_DR is not set.
> > >>
> > >> Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from
> > >> bogus rx timeout interrupt")
> > >> Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
> > >> ---
> > >>   drivers/tty/serial/8250/8250_dw.c | 13 ++++++++++++-
> > >>   1 file changed, 12 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/
> > >> serial/8250/8250_dw.c
> > >> index 07f9be074b4b..1e364280a108 100644
> > >> --- a/drivers/tty/serial/8250/8250_dw.c
> > >> +++ b/drivers/tty/serial/8250/8250_dw.c
> > >> @@ -273,6 +273,7 @@ static int dw8250_handle_irq(struct uart_port *p)
> > >>       unsigned int quirks = d->pdata->quirks;
> > >>       unsigned int status;
> > >>       unsigned long flags;
> > >> +    unsigned char old_fcr;
> > >
> > > No more unsigned char, please. Use u8.
> > >
> > >> @@ -288,9 +289,19 @@ static int dw8250_handle_irq(struct uart_port *p)
> > >>           uart_port_lock_irqsave(p, &flags);
> > >>           status = serial_lsr_in(up);
> > >> -        if (!(status & (UART_LSR_DR | UART_LSR_BI)))
> > >> +        if (!(status & (UART_LSR_DR | UART_LSR_BI))) {
> > >> +            /* To avoid PSLVERR, disable the FIFO first. */
> > >> +            if (up->fcr & UART_FCR_ENABLE_FIFO) {
> > >> +                old_fcr = serial_in(up, UART_FCR);
> >
> > Wait, read(FCR) actually means read(IIR). FCR is write only. Or is DW
> > special in this?
>
> Indeed, the valid bits of the FCR are write-only. It seems that here
> we can only do serial_out(up, UART_FCR, up->fcr); What do you think?

I looked through the DW databook and found that we can use the SFE
register. However, it is not guaranteed that all UARTs in the dw
series have this register.



>
> >
> > >> +                serial_out(up, UART_FCR, old_fcr & ~1);
> > >
> > > s/1/UART_FCR_ENABLE_FIFO/
> > >
> > >> +            }
> > >> +
> > >>               (void) p->serial_in(p, UART_RX);
> > >> +            if (up->fcr & UART_FCR_ENABLE_FIFO)
> > >> +                serial_out(up, UART_FCR, old_fcr);
> > >> +        }
> > >> +
> > >>           uart_port_unlock_irqrestore(p, flags);
> > >>       }
> > >
> > >
> >
> > --
> > js
> > suse labs
> >
>
> Thanks,
> Yunhui

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