linux-kernel - Re: [PATCH 2/2] iommu/amd: Add efr[HATS] max v1 page table level

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Message-ID: <252eb71c-9913-4199-8645-59d8a7513b10@amd.com>
Date: Wed, 30 Apr 2025 17:27:10 +0530
From: Vasant Hegde <vasant.hegde@....com>
To: Ankit Soni <Ankit.Soni@....com>, iommu@...ts.linux.dev
Cc: suravee.suthikulpanit@....com, joro@...tes.org, will@...nel.org,
 robin.murphy@....com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] iommu/amd: Add efr[HATS] max v1 page table level

On 4/23/2025 12:20 PM, Ankit Soni wrote:
> The EFR[HATS] bits indicate maximum host translation level supported by
> IOMMU. Adding support to set the maximum host page table level as indicated
> by EFR[HATS]. If the HATS=11b (reserved), the driver will attempt to use
> guest page table for DMA API.
> 
> Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
> Signed-off-by: Ankit Soni <Ankit.Soni@....com>


Reviewed-by: Vasant Hegde <vasant.hegde@....com>

Minor nit.

> ---
>  drivers/iommu/amd/amd_iommu.h       |  1 +
>  drivers/iommu/amd/amd_iommu_types.h |  1 +
>  drivers/iommu/amd/init.c            | 16 ++++++++++++++++
>  drivers/iommu/amd/io_pgtable.c      |  4 ++--
>  drivers/iommu/amd/iommu.c           |  2 +-
>  5 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
> index bb14c4800dd0..0286120ad4a5 100644
> --- a/drivers/iommu/amd/amd_iommu.h
> +++ b/drivers/iommu/amd/amd_iommu.h
> @@ -42,6 +42,7 @@ int amd_iommu_enable_faulting(unsigned int cpu);
>  extern int amd_iommu_guest_ir;
>  extern enum protection_domain_mode amd_iommu_pgtable;
>  extern int amd_iommu_gpt_level;
> +extern u8 amd_iommu_hpt_level;
>  extern unsigned long amd_iommu_pgsize_bitmap;
>  extern bool amd_iommu_hatdis;
>  
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index 284ff4309660..6bf81197c2c8 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -96,6 +96,7 @@
>  #define FEATURE_GA		BIT_ULL(7)
>  #define FEATURE_HE		BIT_ULL(8)
>  #define FEATURE_PC		BIT_ULL(9)
> +#define FEATURE_HATS		GENMASK_ULL(11, 10)
>  #define FEATURE_GATS		GENMASK_ULL(13, 12)
>  #define FEATURE_GLX		GENMASK_ULL(15, 14)
>  #define FEATURE_GAM_VAPIC	BIT_ULL(21)
> diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
> index f71b236c2af2..c713756fa44e 100644
> --- a/drivers/iommu/amd/init.c
> +++ b/drivers/iommu/amd/init.c
> @@ -152,6 +152,8 @@ bool amd_iommu_dump;
>  bool amd_iommu_irq_remap __read_mostly;
>  
>  enum protection_domain_mode amd_iommu_pgtable = PD_MODE_NONE;
> +/* Host page table level */
> +u8 amd_iommu_hpt_level;
>  /* Guest page table level */
>  int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL;
>  
> @@ -3052,6 +3054,7 @@ static int __init early_amd_iommu_init(void)
>  	struct acpi_table_header *ivrs_base;
>  	int ret;
>  	acpi_status status;
> +	u8 efr_hats;
>  
>  	if (!amd_iommu_detected)
>  		return -ENODEV;
> @@ -3096,6 +3099,19 @@ static int __init early_amd_iommu_init(void)
>  	    FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL)
>  		amd_iommu_gpt_level = PAGE_MODE_5_LEVEL;
>  
> +	efr_hats = FIELD_GET(FEATURE_HATS, amd_iommu_efr);
> +	if (efr_hats != 0x3) {
> +		/*
> +		 * efr[HATS] bits specify the maximum host translation level
> +		 * supported, with LEVEL 4 being initial max level.
> +		 */
> +		amd_iommu_hpt_level = efr_hats + PAGE_MODE_4_LEVEL;
> +	} else {
> +		pr_warn_once("Disable host address translation due to invalid max level (%#x).\n",

s/invalid max level/invalid translation level/

-Vasant