linux-kernel - Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks

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Message-ID: <f9a7c9fd-bd49-4cf0-9a86-a8e65b4fb6a5@oracle.com>
Date: Thu, 1 May 2025 15:20:49 +0530
From: ALOK TIWARI <alok.a.tiwari@...cle.com>
To: Prabhakar <prabhakar.csengg@...il.com>,
        Andrzej Hajda <andrzej.hajda@...el.com>,
        Neil Armstrong <neil.armstrong@...aro.org>,
        Robert Foss <rfoss@...nel.org>,
        Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
        Jonas Karlman <jonas@...boo.se>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
        Maxime Ripard <mripard@...nel.org>,
        Thomas Zimmermann <tzimmermann@...e.de>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Biju Das <biju.das.jz@...renesas.com>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd
 <sboyd@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Magnus Damm <magnus.damm@...il.com>
Cc: dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        linux-clk@...r.kernel.org,
        Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI
 clocks



On 01-05-2025 02:10, Prabhakar wrote:
> From: Lad Prabhakar<prabhakar.mahadev-lad.rj@...renesas.com>
> 
> Add support for PLLDSI and PLLDSI divider clocks.
> 
> Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
> PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
> CPG and DSI drivers.
> 
> The DSI PLL is functionally similar to the CPG's PLLDSI, but has slightly
> different parameter limits and omits the programmable divider present in
> CPG. To ensure precise frequency calculations-especially for milliHz-level
> accuracy needed by the DSI driver-the shared algorithm allows both drivers
> to compute PLL parameters consistently using the same logic and input
> clock.
> 
> Co-developed-by: Fabrizio Castro<fabrizio.castro.jz@...esas.com>
> Signed-off-by: Fabrizio Castro<fabrizio.castro.jz@...esas.com>
> Signed-off-by: Lad Prabhakar<prabhakar.mahadev-lad.rj@...renesas.com>


Acked-by: Alok Tiwari <alok.a.tiwari@...cle.com>

Thanks,
Alok