linux-kernel - Re: [PATCH v2] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error

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Message-ID: <23932150.6Emhk5qWAg@diego>
Date: Thu, 01 May 2025 14:29:41 +0200
From: Heiko Stübner <heiko@...ech.de>
To: vkoul@...nel.org, kishon@...nel.org, cristian.ciocaltea@...labora.com,
 andy.yan@...k-chips.com, Algea Cao <algea.cao@...k-chips.com>
Cc: linux-phy@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org,
 linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
 Algea Cao <algea.cao@...k-chips.com>
Subject:
 Re: [PATCH v2] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz
 error

Am Sonntag, 27. April 2025, 11:51:24 Mitteleuropäische Sommerzeit schrieb Algea Cao:
> When using HDMI PLL frequency division coefficient at 50.25MHz
> that is calculated by rk_hdptx_phy_clk_pll_calc(), it fails to
> get PHY LANE lock. Although the calculated values are within the
> allowable range of PHY PLL configuration.
> 
> In order to fix the PHY LANE lock error and provide the expected
> 50.25MHz output, manually compute the required PHY PLL frequency
> division coefficient and add it to ropll_tmds_cfg configuration
> table.
> 
> Signed-off-by: Algea Cao <algea.cao@...k-chips.com>
> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>

Acked-by: Heiko Stuebner <heiko@...ech.de>