| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20250501-nova-frts-v2-21-b4a137175337@nvidia.com>
Date: Thu, 01 May 2025 21:58:39 +0900
From: Alexandre Courbot <acourbot@...dia.com>
To: Miguel Ojeda <ojeda@...nel.org>, Alex Gaynor <alex.gaynor@...il.com>,
Boqun Feng <boqun.feng@...il.com>, Gary Guo <gary@...yguo.net>,
Björn Roy Baron <bjorn3_gh@...tonmail.com>,
Benno Lossin <benno.lossin@...ton.me>,
Andreas Hindborg <a.hindborg@...nel.org>, Alice Ryhl <aliceryhl@...gle.com>,
Trevor Gross <tmgross@...ch.edu>, Danilo Krummrich <dakr@...nel.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
Jonathan Corbet <corbet@....net>
Cc: John Hubbard <jhubbard@...dia.com>, Ben Skeggs <bskeggs@...dia.com>,
Joel Fernandes <joelagnelf@...dia.com>, Timur Tabi <ttabi@...dia.com>,
Alistair Popple <apopple@...dia.com>, linux-kernel@...r.kernel.org,
rust-for-linux@...r.kernel.org, nouveau@...ts.freedesktop.org,
dri-devel@...ts.freedesktop.org, Alexandre Courbot <acourbot@...dia.com>
Subject: [PATCH v2 21/21] gpu: nova-core: load and run FWSEC-FRTS
With all the required pieces in place, load FWSEC-FRTS onto the GSP
falcon, run it, and check that it completed successfully by carving out
the WPR2 region out of framebuffer memory.
Signed-off-by: Alexandre Courbot <acourbot@...dia.com>
---
drivers/gpu/nova-core/falcon.rs | 3 ---
drivers/gpu/nova-core/gpu.rs | 60 ++++++++++++++++++++++++++++++++++++++++-
drivers/gpu/nova-core/regs.rs | 15 +++++++++++
3 files changed, 74 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 7cae45645e548bab5b85cb53880898cedbae778a..e9ee0c83dfc521db4d48dd92f963daa9fbae0cb2 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -2,9 +2,6 @@
//! Falcon microprocessor base support
-// To be removed when all code is used.
-#![expect(dead_code)]
-
use core::time::Duration;
use hal::FalconHal;
use kernel::bindings;
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index f5ff319db39521cd8ea331bedc27536f7562a5f7..a46768d18ac35158292c3bc2d25c8aca82833391 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -251,7 +251,7 @@ pub(crate) fn new(
let bios = Vbios::new(pdev, &bar)?;
- let _fwsec_frts = FwsecFirmware::new(
+ let fwsec_frts = FwsecFirmware::new(
&gsp_falcon,
pdev.as_ref(),
&bar,
@@ -262,6 +262,64 @@ pub(crate) fn new(
},
)?;
+ // Check that the WPR2 region does not already exists - if it does, the GPU needs to be
+ // reset.
+ if with_bar!(bar, |b| regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI::read(b).hi_val())? != 0 {
+ dev_err!(
+ pdev.as_ref(),
+ "WPR2 region already exists - GPU needs to be reset to proceed\n"
+ );
+ return Err(EBUSY);
+ }
+
+ // Reset falcon, load FWSEC-FRTS, and run it.
+ gsp_falcon.reset(&bar)?;
+ gsp_falcon.dma_load(&bar, &fwsec_frts)?;
+ let (mbox0, _) = gsp_falcon.boot(&bar, Some(0), None)?;
+ if mbox0 != 0 {
+ dev_err!(pdev.as_ref(), "FWSEC firmware returned error {}\n", mbox0);
+ return Err(EINVAL);
+ }
+
+ // SCRATCH_E contains FWSEC-FRTS' error code, if any.
+ let frts_status = with_bar!(bar, |b| regs::NV_PBUS_SW_SCRATCH_0E::read(b)
+ .frts_err_code())?;
+ if frts_status != 0 {
+ dev_err!(
+ pdev.as_ref(),
+ "FWSEC-FRTS returned with error code {:#x}",
+ frts_status
+ );
+ return Err(EINVAL);
+ }
+
+ // Check the WPR2 has been created as we requested.
+ let (wpr2_lo, wpr2_hi) = with_bar!(bar, |b| {
+ (
+ (regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO::read(b).lo_val() as u64) << 12,
+ (regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI::read(b).hi_val() as u64) << 12,
+ )
+ })?;
+ if wpr2_hi == 0 {
+ dev_err!(
+ pdev.as_ref(),
+ "WPR2 region not created after running FWSEC-FRTS\n"
+ );
+
+ return Err(ENOTTY);
+ } else if wpr2_lo != fb_layout.frts.start {
+ dev_err!(
+ pdev.as_ref(),
+ "WPR2 region created at unexpected address {:#x} ; expected {:#x}\n",
+ wpr2_lo,
+ fb_layout.frts.start,
+ );
+ return Err(EINVAL);
+ }
+
+ dev_info!(pdev.as_ref(), "WPR2: {:#x}-{:#x}\n", wpr2_lo, wpr2_hi);
+ dev_info!(pdev.as_ref(), "GPU instance built\n");
+
Ok(pin_init!(Self {
spec,
bar,
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 15ec9b7e69694ff198b5353d562fc1aff5eefd3f..3acec36f2d5701af4a752808e86d71d5f200359b 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -43,6 +43,13 @@ pub(crate) fn chipset(self) -> Result<Chipset, Error> {
}
}
+/* PBUS */
+
+// TODO: this is an array of registers.
+register!(NV_PBUS_SW_SCRATCH_0E@...0001438 {
+ 31:16 frts_err_code as u16;
+});
+
/* PFB */
register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR @ 0x00100c10 {
@@ -59,6 +66,14 @@ pub(crate) fn chipset(self) -> Result<Chipset, Error> {
30:30 ecc_mode_enabled as bool;
});
+register!(NV_PFB_PRI_MMU_WPR2_ADDR_LO@...01fa824 {
+ 31:4 lo_val as u32;
+});
+
+register!(NV_PFB_PRI_MMU_WPR2_ADDR_HI@...01fa828 {
+ 31:4 hi_val as u32;
+});
+
/* PGC6 */
register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128 {
--
2.49.0
Powered by blists - more mailing lists