linux-kernel - Re: [PATCH v2 15/22] arm64: Disable GICv5 read/write/instruction traps

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Message-ID: <86seloh04u.wl-maz@kernel.org>
Date: Thu, 01 May 2025 15:32:49 +0100
From: Marc Zyngier <maz@...nel.org>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will@...nel.org>,
	Arnd Bergmann <arnd@...db.de>,
	Sascha Bischoff <sascha.bischoff@....com>,
	Timothy Hayes <timothy.hayes@....com>,
	"Liam R. Howlett" <Liam.Howlett@...cle.com>,
	Mark Rutland <mark.rutland@....com>,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org
Subject: Re: [PATCH v2 15/22] arm64: Disable GICv5 read/write/instruction traps

On Thu, 24 Apr 2025 11:25:26 +0100,
Lorenzo Pieralisi <lpieralisi@...nel.org> wrote:
> 
> GICv5 trap configuration registers value is UNKNOWN at reset.
> 
> Initialize GICv5 EL2 trap configuration registers to prevent
> trapping GICv5 instruction/register access upon entering the
> kernel.
> 
> Signed-off-by: Lorenzo Pieralisi <lpieralisi@...nel.org>
> Cc: Will Deacon <will@...nel.org>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Marc Zyngier <maz@...nel.org>
> ---
>  arch/arm64/include/asm/el2_setup.h | 45 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index ebceaae3c749b84395c9c5eccf0caf874697ad11..1e362bb3b042d51fff15a7c2abc73842930b275a 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -165,6 +165,50 @@
>  .Lskip_gicv3_\@:
>  .endm
>  
> +/* GICv5 system register access */
> +.macro __init_el2_gicv5
> +	mrs_s	x0, SYS_ID_AA64PFR2_EL1
> +	ubfx	x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4
> +	cbz	x0, .Lskip_gicv5_\@
> +
> +	mov	x0, #(1 << ICH_HFGITR_EL2_GICRCDNMIA_SHIFT	| \
> +		      1 << ICH_HFGITR_EL2_GICRCDIA_SHIFT	| \
> +		      1 << ICH_HFGITR_EL2_GICCDDI_SHIFT		| \
> +		      1 << ICH_HFGITR_EL2_GICCDEOI_SHIFT	| \
> +		      1 << ICH_HFGITR_EL2_GICCDHM_SHIFT		| \
> +		      1 << ICH_HFGITR_EL2_GICCRDRCFG_SHIFT	| \
> +		      1 << ICH_HFGITR_EL2_GICCDPEND_SHIFT	| \
> +		      1 << ICH_HFGITR_EL2_GICCDAFF_SHIFT	| \
> +		      1 << ICH_HFGITR_EL2_GICCDPRI_SHIFT	| \
> +		      1 << ICH_HFGITR_EL2_GICCDDIS_SHIFT	| \
> +		      1 << ICH_HFGITR_EL2_GICCDEN_SHIFT)

Please write this as:

	mov	x0, #(ICH_HFGITR_EL2_GICRCDNMIA	| \
		      ICH_HFGITR_EL2_GICRCDIA	| \
		      ICH_HFGITR_EL2_GICCDDI	| \
		      ICH_HFGITR_EL2_GICCDEOI	| \
		      ICH_HFGITR_EL2_GICCDHM	| \
		      ICH_HFGITR_EL2_GICCRDRCFG	| \
		      ICH_HFGITR_EL2_GICCDPEND	| \
		      ICH_HFGITR_EL2_GICCDAFF	| \
		      ICH_HFGITR_EL2_GICCDPRI	| \
		      ICH_HFGITR_EL2_GICCDDIS	| \
		      ICH_HFGITR_EL2_GICCDEN)

which has the exact same effect, and is consistent with other uses in
this file.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.