linux-kernel - Re: [PATCH 1/5] riscv: misaligned: factorize trap handling

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Message-ID: <alpine.DEB.2.21.2505012150460.31828@angie.orcam.me.uk>
Date: Thu, 1 May 2025 21:51:54 +0100 (BST)
From: "Maciej W. Rozycki" <macro@...am.me.uk>
To: Clément Léger <cleger@...osinc.com>
cc: Peter Zijlstra <peterz@...radead.org>, Alexandre Ghiti <alex@...ti.fr>, 
    "open list:DOCUMENTATION" <linux-doc@...r.kernel.org>, 
    open list <linux-kernel@...r.kernel.org>, 
    "open list:RISC-V ARCHITECTURE" <linux-riscv@...ts.infradead.org>, 
    "open list:KERNEL SELFTEST FRAMEWORK" <linux-kselftest@...r.kernel.org>, 
    Jonathan Corbet <corbet@....net>, Paul Walmsley <paul.walmsley@...ive.com>, 
    Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
    Shuah Khan <shuah@...nel.org>, Andrew Jones <ajones@...tanamicro.com>, 
    Samuel Holland <samuel.holland@...ive.com>
Subject: Re: [PATCH 1/5] riscv: misaligned: factorize trap handling

On Thu, 1 May 2025, Maciej W. Rozycki wrote:

>  Hopefully not in the hardirq context though, and the usual approach is to 
> keep interrupts disabled in the emulation path if arriving from the kernel 
> mode as we don't expect kernel code to be ever paged out (the same applies 
> to all kinds of machine instruction emulation).

 s/code/data/, obviously.

  Maciej