linux-kernel - [PATCH v3 2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine

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Message-ID: <20250502033451.2291330-3-devarsht@ti.com>
Date: Fri, 2 May 2025 09:04:51 +0530
From: Devarsh Thakkar <devarsht@...com>
To: <vkoul@...nel.org>, <kishon@...nel.org>, <mripard@...nel.org>,
        <linux-phy@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
CC: <sakari.ailus@...ux.intel.com>, <u.kleine-koenig@...libre.com>,
        <vigneshr@...com>, <aradhya.bhatia@...ux.dev>, <s-jain1@...com>,
        <r-donadkar@...com>, <tomi.valkeinen@...asonboard.com>,
        <devarsht@...com>
Subject: [PATCH v3 2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine

Do read-modify-write so that we re-use the characterized reset value as
specified in TRM [1] to program calibration wait time which defines number
of cycles to wait for after startup state machine is in bandgap enable
state.

This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's
AM62L and J721E SoC [2].

[1] AM62P TRM (Section ): https://www.ti.com/lit/pdf/spruj83

[2]: Link:
https://gist.github.com/devarsht/89e4830e886774fcd50aa6e29cce3a79

Cc: stable@...r.kernel.org
Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support")
Signed-off-by: Devarsh Thakkar <devarsht@...com>
---
V3: Do read-modify-write to preserve reset value for calibration wait time
V2: Introduced this as as separate patch

 drivers/phy/cadence/cdns-dphy.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
index a94109a63788..2e28c56c4bdd 100644
--- a/drivers/phy/cadence/cdns-dphy.c
+++ b/drivers/phy/cadence/cdns-dphy.c
@@ -30,6 +30,7 @@
 
 #define DPHY_CMN_SSM			DPHY_PMA_CMN(0x20)
 #define DPHY_CMN_SSM_EN			BIT(0)
+#define DPHY_CMN_SSM_CAL_WAIT_TIME	GENMASK(8, 1)
 #define DPHY_CMN_TX_MODE_EN		BIT(9)
 
 #define DPHY_CMN_PWM			DPHY_PMA_CMN(0x40)
@@ -421,7 +422,8 @@ static int cdns_dphy_power_on(struct phy *phy)
 	writel(reg, dphy->regs + DPHY_BAND_CFG);
 
 	/* Start TX state machine. */
-	writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
+	reg = readl(dphy->regs + DPHY_CMN_SSM);
+	writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
 	       dphy->regs + DPHY_CMN_SSM);
 
 	ret = cdns_dphy_wait_for_pll_lock(dphy);
-- 
2.39.1