lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <aBURK58syHRV9Eqx@google.com>
Date: Fri, 2 May 2025 11:38:35 -0700
From: Namhyung Kim <namhyung@...nel.org>
To: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Ian Rogers <irogers@...gle.com>, Kan Liang <kan.liang@...ux.intel.com>,
	Jiri Olsa <jolsa@...nel.org>,
	Adrian Hunter <adrian.hunter@...el.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Ingo Molnar <mingo@...nel.org>, LKML <linux-kernel@...r.kernel.org>,
	linux-perf-users@...r.kernel.org,
	Ravi Bangoria <ravi.bangoria@....com>, Leo Yan <leo.yan@....com>
Subject: Re: [PATCH 11/11] perf mem: Add 'dtlb' output field

On Fri, May 02, 2025 at 01:30:35PM -0300, Arnaldo Carvalho de Melo wrote:
> On Wed, Apr 30, 2025 at 01:55:48PM -0700, Namhyung Kim wrote:
> > This is a breakdown of perf_mem_data_src.mem_dtlb values.  It assumes
> > PMU drivers would set PERF_MEM_TLB_HIT bit with an appropriate level.
> > And having PERF_MEM_TLB_MISS means that it failed to find one in any
> > levels of TLB.  For now, it doesn't use PERF_MEM_TLB_{WK,OS} bits.
> > 
> > Also it seems Intel machines don't distinguish L1 or L2 precisely.  So I
> > added ANY_HIT (printed as "L?-Hit") to handle the case.
> > 
> >   $ perf mem report -F overhead,dtlb,dso --stdio
> >   ...
> >   #           --- D-TLB ----
> >   # Overhead   L?-Hit   Miss  Shared Object
> >   # ........  ..............  .................
> >   #
> >       67.03%    99.5%   0.5%  [unknown]
> >       31.23%    99.2%   0.8%  [kernel.kallsyms]
> >        1.08%    97.8%   2.2%  [i915]
> >        0.36%   100.0%   0.0%  [JIT] tid 6853
> >        0.12%   100.0%   0.0%  [drm]
> >        0.05%   100.0%   0.0%  [drm_kms_helper]
> >        0.05%   100.0%   0.0%  [ext4]
> >        0.02%   100.0%   0.0%  [aesni_intel]
> >        0.02%   100.0%   0.0%  [crc32c_intel]
> >        0.02%   100.0%   0.0%  [dm_crypt]
> >        ...
> 
> root@...ber:~# perf report --header | grep cpudesc
> # cpudesc : AMD Ryzen 9 9950X3D 16-Core Processor
> root@...ber:~# perf mem report -F overhead,dtlb,dso --stdio | head -20
> # To display the perf.data header info, please use --header/--header-only options.
> #
> #
> # Total Lost Samples: 0
> #
> # Samples: 2K of event 'cycles:P'
> # Total weight : 2637
> # Sort order   : local_weight,mem,sym,dso,symbol_daddr,dso_daddr,snoop,tlb,locked,blocked,local_ins_lat,local_p_stage_cyc
> #
> #           ---------- D-TLB -----------                                   
> # Overhead   L1-Hit L2-Hit   Miss  Other  Shared Object                    
> # ........  ............................  .................................
> #
>     77.47%    18.4%   0.1%   0.6%  80.9%  [kernel.kallsyms]                
>      5.61%    36.5%   0.7%   1.4%  61.5%  libxul.so                        
>      2.77%    39.7%   0.0%  12.3%  47.9%  libc.so.6                        
>      2.01%    34.0%   1.9%   1.9%  62.3%  libglib-2.0.so.0.8400.1          
>      1.93%    31.4%   2.0%   2.0%  64.7%  [amdgpu]                         
>      1.63%    48.8%   0.0%   0.0%  51.2%  [JIT] tid 60168                  
>      1.14%     3.3%   0.0%   0.0%  96.7%  [vdso]                           
> root@...ber:~#

I guess it's because those samples don't have mem_info as they are not
memory instructions.

Can you please re-run the perf record with filters like below?

  $ perf record -aW --sample-mem-info -e cycles:P --filter 'mem_op == load || mem_op == store' sleep 1

Thanks,
Namhyung


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ