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Message-Id: <20250503-topic-8280_slpi-v1-2-9400a35574f7@oss.qualcomm.com>
Date: Sat, 03 May 2025 00:38:00 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Konrad Dybcio <konradybcio@...nel.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, linux-remoteproc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH 2/3] arm64: dts: qcom: sc8280xp: Fix node order
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Certain /soc@0 subnodes are very out of order. Reshuffle them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 574 ++++++++++++++++-----------------
1 file changed, 287 insertions(+), 287 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 35ef31d4ecf26125407bb64dd2de6e777a3400a3..3f9195da90ee898c68296f19dc55bcb3ac73fe29 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2454,293 +2454,6 @@ tcsr: syscon@...0000 {
reg = <0x0 0x01fc0000 0x0 0x30000>;
};
- gpu: gpu@...0000 {
- compatible = "qcom,adreno-690.0", "qcom,adreno";
-
- reg = <0 0x03d00000 0 0x40000>,
- <0 0x03d9e000 0 0x1000>,
- <0 0x03d61000 0 0x800>;
- reg-names = "kgsl_3d0_reg_memory",
- "cx_mem",
- "cx_dbgc";
- interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
- operating-points-v2 = <&gpu_opp_table>;
-
- qcom,gmu = <&gmu>;
- interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
- interconnect-names = "gfx-mem";
- #cooling-cells = <2>;
-
- status = "disabled";
-
- gpu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-270000000 {
- opp-hz = /bits/ 64 <270000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
- opp-peak-kBps = <451000>;
- };
-
- opp-410000000 {
- opp-hz = /bits/ 64 <410000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
- opp-peak-kBps = <1555000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
- opp-peak-kBps = <1555000>;
- };
-
- opp-547000000 {
- opp-hz = /bits/ 64 <547000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
- opp-peak-kBps = <1555000>;
- };
-
- opp-606000000 {
- opp-hz = /bits/ 64 <606000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
- opp-peak-kBps = <2736000>;
- };
-
- opp-640000000 {
- opp-hz = /bits/ 64 <640000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
- opp-peak-kBps = <2736000>;
- };
-
- opp-655000000 {
- opp-hz = /bits/ 64 <655000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
- opp-peak-kBps = <2736000>;
- };
-
- opp-690000000 {
- opp-hz = /bits/ 64 <690000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
- opp-peak-kBps = <2736000>;
- };
- };
- };
-
- gmu: gmu@...a000 {
- compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
- reg = <0 0x03d6a000 0 0x34000>,
- <0 0x03de0000 0 0x10000>,
- <0 0x0b290000 0 0x10000>;
- reg-names = "gmu", "rscc", "gmu_pdc";
- interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hfi", "gmu";
- clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
- <&gpucc GPU_CC_CXO_CLK>,
- <&gcc GCC_DDRSS_GPU_AXI_CLK>,
- <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
- <&gpucc GPU_CC_AHB_CLK>,
- <&gpucc GPU_CC_HUB_CX_INT_CLK>,
- <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
- clock-names = "gmu",
- "cxo",
- "axi",
- "memnoc",
- "ahb",
- "hub",
- "smmu_vote";
- power-domains = <&gpucc GPU_CC_CX_GDSC>,
- <&gpucc GPU_CC_GX_GDSC>;
- power-domain-names = "cx",
- "gx";
- iommus = <&gpu_smmu 5 0xc00>;
- operating-points-v2 = <&gmu_opp_table>;
-
- gmu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
- };
- };
- };
-
- gpucc: clock-controller@...0000 {
- compatible = "qcom,sc8280xp-gpucc";
- reg = <0 0x03d90000 0 0x9000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_GPU_GPLL0_CLK_SRC>,
- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
- clock-names = "bi_tcxo",
- "gcc_gpu_gpll0_clk_src",
- "gcc_gpu_gpll0_div_clk_src";
-
- power-domains = <&rpmhpd SC8280XP_GFX>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
- gpu_smmu: iommu@...0000 {
- compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
- "qcom,smmu-500", "arm,mmu-500";
- reg = <0 0x03da0000 0 0x20000>;
- #iommu-cells = <2>;
- #global-interrupts = <2>;
- interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
- <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
- <&gpucc GPU_CC_AHB_CLK>,
- <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
- <&gpucc GPU_CC_CX_GMU_CLK>,
- <&gpucc GPU_CC_HUB_CX_INT_CLK>,
- <&gpucc GPU_CC_HUB_AON_CLK>;
- clock-names = "gcc_gpu_memnoc_gfx_clk",
- "gcc_gpu_snoc_dvm_gfx_clk",
- "gpu_cc_ahb_clk",
- "gpu_cc_hlos1_vote_gpu_smmu_clk",
- "gpu_cc_cx_gmu_clk",
- "gpu_cc_hub_cx_int_clk",
- "gpu_cc_hub_aon_clk";
-
- power-domains = <&gpucc GPU_CC_CX_GDSC>;
- dma-coherent;
- };
-
- usb_0_hsphy: phy@...5000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e5000 0 0x400>;
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy0: phy@...7000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e7000 0 0x400>;
- clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy1: phy@...8000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e8000 0 0x400>;
- clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy2: phy@...9000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e9000 0 0x400>;
- clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy3: phy@...a000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088ea000 0 0x400>;
- clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_qmpphy0: phy@...f000 {
- compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
- reg = <0 0x088ef000 0 0x2000>;
-
- clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
- <&gcc GCC_USB3_MP0_CLKREF_CLK>,
- <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
- <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
- clock-names = "aux", "ref", "com_aux", "pipe";
-
- resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
- <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
- reset-names = "phy", "phy_phy";
-
- power-domains = <&gcc USB30_MP_GDSC>;
-
- #clock-cells = <0>;
- clock-output-names = "usb2_phy0_pipe_clk";
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_qmpphy1: phy@...1000 {
- compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
- reg = <0 0x088f1000 0 0x2000>;
-
- clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
- <&gcc GCC_USB3_MP1_CLKREF_CLK>,
- <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
- <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
- clock-names = "aux", "ref", "com_aux", "pipe";
-
- resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
- <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
- reset-names = "phy", "phy_phy";
-
- power-domains = <&gcc USB30_MP_GDSC>;
-
- #clock-cells = <0>;
- clock-output-names = "usb2_phy1_pipe_clk";
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
remoteproc_adsp: remoteproc@...0000 {
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x10000>;
@@ -3166,6 +2879,180 @@ lpasscc: clock-controller@...0000 {
#reset-cells = <1>;
};
+ gpu: gpu@...0000 {
+ compatible = "qcom,adreno-690.0", "qcom,adreno";
+
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <451000>;
+ };
+
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-547000000 {
+ opp-hz = /bits/ 64 <547000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-606000000 {
+ opp-hz = /bits/ 64 <606000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-640000000 {
+ opp-hz = /bits/ 64 <640000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-655000000 {
+ opp-hz = /bits/ 64 <655000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-690000000 {
+ opp-hz = /bits/ 64 <690000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <2736000>;
+ };
+ };
+ };
+
+ gmu: gmu@...a000 {
+ compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x03de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&gpu_smmu 5 0xc00>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@...0000 {
+ compatible = "qcom,sc8280xp-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+
+ power-domains = <&rpmhpd SC8280XP_GFX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ gpu_smmu: iommu@...0000 {
+ compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ dma-coherent;
+ };
+
sdc2: mmc@...4000 {
compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -3209,6 +3096,71 @@ opp-202000000 {
};
};
+ usb_0_hsphy: phy@...5000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e5000 0 0x400>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy0: phy@...7000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e7000 0 0x400>;
+ clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy1: phy@...8000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e8000 0 0x400>;
+ clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy2: phy@...9000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e9000 0 0x400>;
+ clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy3: phy@...a000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088ea000 0 0x400>;
+ clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
usb_0_qmpphy: phy@...b000 {
compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
reg = <0 0x088eb000 0 0x4000>;
@@ -3256,6 +3208,54 @@ port@2 {
};
};
+ usb_2_qmpphy0: phy@...f000 {
+ compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
+ reg = <0 0x088ef000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_MP0_CLKREF_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_qmpphy1: phy@...1000 {
+ compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
+ reg = <0 0x088f1000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_MP1_CLKREF_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
usb_1_hsphy: phy@...2000 {
compatible = "qcom,sc8280xp-usb-hs-phy",
"qcom,usb-snps-hs-5nm-phy";
--
2.49.0
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