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Message-ID: <20250502004328-GYA427222@gentoo>
Date: Fri, 2 May 2025 00:43:28 +0000
From: Yixun Lan <dlan@...too.org>
To: Inochi Amaoto <inochiama@...il.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
Chen Wang <unicorn_wang@...look.com>,
Alexander Sverdlin <alexander.sverdlin@...il.com>,
Thomas Bonnefille <thomas.bonnefille@...tlin.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
sophgo@...ts.linux.dev, linux-kernel@...r.kernel.org,
Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH 1/4] riscv: dts: sophgo: Move all soc specific device
into soc dtsi file
On 09:26 Wed 30 Apr , Inochi Amaoto wrote:
> Although the cv1800b/cv1812h/sg2000/sg2002 share most peripherals,
> some basic peripherals, like clock, pinctrl, clint and plint, are
> not shared. These are caused by not only historical reason (plic,
> clint), but also the fact the device is not the same (clock, pinctrl).
>
> It is good to override device compatible when the soc number is small,
~~~SoC, we usually
> but now it is a burden for maintenance, and it is kind of annoyed to
> explain why using override. So it is time to move this out of the
> common peripheral header.
>
> Move all soc related peripherla device from common peripheral header
~~~~~~~~~~typo, peripheral
> to the soc specific header to get rid of most compatible override.
>
> Signed-off-by: Inochi Amaoto <inochiama@...il.com>
otherwise, looks good
Reviewed-by: Yixun Lan <dlan@...too.org>
> ---
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 38 +++++++++++++++++--------
> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 38 +++++++++++++++++--------
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 --------------
> arch/riscv/boot/dts/sophgo/sg2002.dtsi | 38 +++++++++++++++++--------
> 4 files changed, 78 insertions(+), 58 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index aa1f5df100f0..fc9e6b56790f 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -15,23 +15,37 @@ memory@...00000 {
> };
>
> soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
> +
> pinctrl: pinctrl@...1000 {
> compatible = "sophgo,cv1800b-pinctrl";
> reg = <0x03001000 0x1000>,
> <0x05027000 0x1000>;
> reg-names = "sys", "rtc";
> };
> +
> + clk: clock-controller@...2000 {
> + compatible = "sophgo,cv1800-clk";
> + reg = <0x03002000 0x1000>;
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
> + plic: interrupt-controller@...00000 {
> + compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@...00000 {
> + compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
> };
> -
> -&plic {
> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> -};
> -
> -&clint {
> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> -};
> -
> -&clk {
> - compatible = "sophgo,cv1800-clk";
> -};
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> index 8a1b95c5116b..fcea4376fb79 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> @@ -17,23 +17,37 @@ memory@...00000 {
> };
>
> soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
> +
> pinctrl: pinctrl@...1000 {
> compatible = "sophgo,cv1812h-pinctrl";
> reg = <0x03001000 0x1000>,
> <0x05027000 0x1000>;
> reg-names = "sys", "rtc";
> };
> +
> + clk: clock-controller@...2000 {
> + compatible = "sophgo,cv1810-clk";
> + reg = <0x03002000 0x1000>;
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
> + plic: interrupt-controller@...00000 {
> + compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@...00000 {
> + compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
> };
> -
> -&plic {
> - compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> -};
> -
> -&clint {
> - compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> -};
> -
> -&clk {
> - compatible = "sophgo,cv1810-clk";
> -};
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index c18822ec849f..805b694aa814 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -49,18 +49,10 @@ osc: oscillator {
>
> soc {
> compatible = "simple-bus";
> - interrupt-parent = <&plic>;
> #address-cells = <1>;
> #size-cells = <1>;
> - dma-noncoherent;
> ranges;
>
> - clk: clock-controller@...2000 {
> - reg = <0x03002000 0x1000>;
> - clocks = <&osc>;
> - #clock-cells = <1>;
> - };
> -
> gpio0: gpio@...0000 {
> compatible = "snps,dw-apb-gpio";
> reg = <0x3020000 0x1000>;
> @@ -344,19 +336,5 @@ dmac: dma-controller@...0000 {
> snps,data-width = <4>;
> status = "disabled";
> };
> -
> - plic: interrupt-controller@...00000 {
> - reg = <0x70000000 0x4000000>;
> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <2>;
> - riscv,ndev = <101>;
> - };
> -
> - clint: timer@...00000 {
> - reg = <0x74000000 0x10000>;
> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> - };
> };
> };
> diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> index 7f79de33163c..df133831bd3e 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> @@ -17,27 +17,41 @@ memory@...00000 {
> };
>
> soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
> +
> pinctrl: pinctrl@...1000 {
> compatible = "sophgo,sg2002-pinctrl";
> reg = <0x03001000 0x1000>,
> <0x05027000 0x1000>;
> reg-names = "sys", "rtc";
> };
> +
> + clk: clock-controller@...2000 {
> + compatible = "sophgo,sg2000-clk";
> + reg = <0x03002000 0x1000>;
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
> + plic: interrupt-controller@...00000 {
> + compatible = "sophgo,sg2002-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@...00000 {
> + compatible = "sophgo,sg2002-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
> };
>
> -&plic {
> - compatible = "sophgo,sg2002-plic", "thead,c900-plic";
> -};
> -
> -&clint {
> - compatible = "sophgo,sg2002-clint", "thead,c900-clint";
> -};
> -
> -&clk {
> - compatible = "sophgo,sg2000-clk";
> -};
> -
> &sdhci0 {
> compatible = "sophgo,sg2002-dwcmshc";
> };
> --
> 2.49.0
>
--
Yixun Lan (dlan)
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