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Message-ID: <aBRtNOLQ6R-5iOB4@ryzen>
Date: Fri, 2 May 2025 08:59:00 +0200
From: Niklas Cassel <cassel@...nel.org>
To: Wilfred Mallawa <wilfred.opensource@...il.com>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Heiko Stuebner <heiko@...ech.de>,
Philipp Zabel <p.zabel@...gutronix.de>,
Damien Le Moal <dlemoal@...nel.org>,
Alistair Francis <alistair@...stair23.me>,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
Wilfred Mallawa <wilfred.mallawa@....com>
Subject: Re: [PATCH v2] PCI: dwc: Add support for slot reset on link down
event
Hello Wilfred,
On Thu, May 01, 2025 at 11:57:39AM +1000, Wilfred Mallawa wrote:
> @@ -688,6 +699,79 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> return ret;
> }
>
> +static int rockchip_pcie_rc_reset_slot(struct pci_host_bridge *bridge,
> + struct pci_dev *pdev)
> +{
> + struct pci_bus *bus = bridge->bus;
> + struct dw_pcie_rp *pp = bus->sysdata;
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
> + struct device *dev = rockchip->pci.dev;
> + u32 val;
> + int ret;
> +
> + dw_pcie_stop_link(pci);
> + rockchip_pcie_phy_deinit(rockchip);
> + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
Sorry that I didn't see/mention this earlier, but the order which we deinit
things should be the reversed order of how we initialized things.
(i.e. it should match the ordering of the error path.)
In both the error path of this function, and the error path of
rockchip_pcie_probe(), we do deinit_clk before deinit_phy, so I suggest we
do the same here.
Kind regards,
Niklas
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