| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAK9=C2VOxFJVfZxCPBi-79ZynexTMCa4nHinbH_MNt3Bdm-arg@mail.gmail.com>
Date: Fri, 2 May 2025 14:45:08 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Rob Herring <robh@...nel.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Jassi Brar <jassisinghbrar@...il.com>, Thomas Gleixner <tglx@...utronix.de>,
"Rafael J . Wysocki" <rafael@...nel.org>, Mika Westerberg <mika.westerberg@...ux.intel.com>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Linus Walleij <linus.walleij@...aro.org>, Bartosz Golaszewski <brgl@...ev.pl>,
Uwe Kleine-König <ukleinek@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <paul.walmsley@...ive.com>,
Len Brown <lenb@...nel.org>, Sunil V L <sunilvl@...tanamicro.com>,
Rahul Pathak <rpathak@...tanamicro.com>, Leyfoon Tan <leyfoon.tan@...rfivetech.com>,
Atish Patra <atishp@...shpatra.org>, Andrew Jones <ajones@...tanamicro.com>,
Samuel Holland <samuel.holland@...ive.com>, Anup Patel <anup@...infault.org>,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH v2 02/17] dt-bindings: mailbox: Add bindings for RPMI
shared memory transport
On Tue, Feb 4, 2025 at 4:00 AM Rob Herring <robh@...nel.org> wrote:
>
> On Mon, Feb 03, 2025 at 02:18:51PM +0530, Anup Patel wrote:
> > Add device tree bindings for the common RISC-V Platform Management
> > Interface (RPMI) shared memory transport as a mailbox controller.
> >
> > Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> > ---
> > .../mailbox/riscv,rpmi-shmem-mbox.yaml | 150 ++++++++++++++++++
> > 1 file changed, 150 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
> > new file mode 100644
> > index 000000000000..c339df5d9e24
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml
> > @@ -0,0 +1,150 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: RISC-V Platform Management Interface (RPMI) shared memory mailbox
> > +
> > +maintainers:
> > + - Anup Patel <anup@...infault.org>
> > +
> > +description: |
> > + The RISC-V Platform Management Interface (RPMI) [1] defines a common shared
> > + memory based RPMI transport. This RPMI shared memory transport integrates as
> > + mailbox controller in the SBI implementation or supervisor software whereas
> > + each RPMI service group is mailbox client in the SBI implementation and
> > + supervisor software.
> > +
> > + ===========================================
> > + References
> > + ===========================================
> > +
> > + [1] RISC-V Platform Management Interface (RPMI)
> > + https://github.com/riscv-non-isa/riscv-rpmi/releases
> > +
> > +properties:
> > + compatible:
> > + const: riscv,rpmi-shmem-mbox
> > +
> > + reg:
> > + oneOf:
> > + - items:
> > + - description: A2P request queue base address
> > + - description: P2A acknowledgment queue base address
> > + - description: P2A request queue base address
> > + - description: A2P acknowledgment queue base address
> > + - description: A2P doorbell address
> > + - items:
> > + - description: A2P request queue base address
> > + - description: P2A acknowledgment queue base address
> > + - description: P2A request queue base address
> > + - description: A2P acknowledgment queue base address
> > + - items:
> > + - description: A2P request queue base address
> > + - description: P2A acknowledgment queue base address
> > + - description: A2P doorbell address
> > + - items:
> > + - description: A2P request queue base address
> > + - description: P2A acknowledgment queue base address
> > +
> > + reg-names:
> > + oneOf:
> > + - items:
> > + - const: a2p-req
> > + - const: p2a-ack
> > + - const: p2a-req
> > + - const: a2p-ack
> > + - const: doorbell
> > + - items:
> > + - const: a2p-req
> > + - const: p2a-ack
> > + - const: p2a-req
> > + - const: a2p-ack
>
> These first 2 items lists can be combined with the addition of
> 'minItems: 4'
It seems "minItems" is not allowed under "items".
If we put "minItems: 4" under "reg-names" then below
combinations become invalid.
>
> > + - items:
> > + - const: a2p-req
> > + - const: p2a-ack
> > + - const: doorbell
> > + - items:
> > + - const: a2p-req
> > + - const: p2a-ack
> > +
> > + interrupts:
> > + maxItems: 1
> > + description:
> > + The RPMI shared memory transport supports wired interrupt specified by
> > + this property as the P2A doorbell.
> > +
> > + msi-parent:
> > + description:
> > + The RPMI shared memory transport supports MSI as P2A doorbell and this
> > + property specifies the target MSI controller.
> > +
> > + riscv,slot-size:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + minimum: 64
> > + description:
> > + Power-of-2 RPMI slot size of the RPMI shared memory transport.
> > +
> > + riscv,doorbell-mask:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0xffffffff
> > + description:
> > + Update only the register bits of doorbell defined by the mask (32 bit).
> > +
> > + riscv,doorbell-value:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0x1
> > + description:
> > + Value written to the doorbell register bits (32-bit access) specified
> > + by the riscv,db-mask property.
>
> You mean riscv,doorbell-mask?
>
> I'm confused why you would need both? If the value to write is fixed
> here, then why do you need a mask? You could just mask the value here.
>
> I assume there's some dependency between these 2 properties. That needs
> to be captured with 'dependencies'.
We don't need the "riscv,doorbell-mask" property because the
latest frozen RPMI specification only defines a write-only 32-bit
doorbell register. I will remove this property in the next revision.
>
> > +
> > + "#mbox-cells":
> > + const: 1
> > + description:
> > + The first cell specifies RPMI service group ID.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - riscv,slot-size
> > + - "#mbox-cells"
> > +
> > +anyOf:
> > + - required:
> > + - interrupts
> > + - required:
> > + - msi-parent
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + // Example 1 (RPMI shared memory with only 2 queues):
> > + mailbox@...80000 {
> > + compatible = "riscv,rpmi-shmem-mbox";
> > + reg = <0x10080000 0x10000>,
> > + <0x10090000 0x10000>,
> > + <0x100a0000 0x4>;
> > + reg-names = "a2p-req", "p2a-ack", "doorbell";
> > + msi-parent = <&imsic_mlevel>;
> > + riscv,slot-size = <64>;
> > + #mbox-cells = <1>;
> > + };
> > + - |
> > + // Example 2 (RPMI shared memory with only 4 queues):
> > + mailbox@...01000 {
> > + compatible = "riscv,rpmi-shmem-mbox";
> > + reg = <0x10001000 0x800>,
> > + <0x10001800 0x800>,
> > + <0x10002000 0x800>,
> > + <0x10002800 0x800>,
> > + <0x10003000 0x4>;
> > + reg-names = "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "doorbell";
> > + msi-parent = <&imsic_mlevel>;
> > + riscv,slot-size = <64>;
> > + riscv,doorbell-mask = <0x00008000>;
> > + riscv,doorbell-value = <0x00008000>;
> > + #mbox-cells = <1>;
> > + };
> > --
> > 2.43.0
> >
Regards,
Anup
Powered by blists - more mailing lists