lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <CAMuHMdVh+Xr2o7YMPpk3gwYDAD8z-W0OOWO=2Gq0VunyaoH-tA@mail.gmail.com>
Date: Fri, 2 May 2025 13:42:46 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Linus Walleij <linus.walleij@...aro.org>, Magnus Damm <magnus.damm@...il.com>, 
	linux-renesas-soc@...r.kernel.org, linux-gpio@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v3] pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC

On Tue, 15 Apr 2025 at 15:09, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Add pinctrl support for the Renesas RZ/V2N SoC by reusing the existing
> RZ/V2H(P) pin configuration data. The PFC block is nearly identical, with
> the only difference being the absence of `PCIE1_RSTOUTB` on RZ/V2N.
>
> To handle this, the rzv2h_dedicated_pins array is refactored into a common
> and pcie1 subset. This enables reuse of the common portion across both
> SoCs, while excluding PCIE1_RSTOUTB for RZ/V2N.
>
> This change allows the pinctrl-rzg2l driver to support RZ/V2N without
> duplicating large parts of the RZ/V2H configuration.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> Hi All,
> This patch is from series [0]. Since most of the patches have already
> been queued, I'm sending this one separately.
> [0] https://lore.kernel.org/all/20250407191628.323613-11-prabhakar.mahadev-lad.rj@bp.renesas.com/
> Cheers, Prabhakar
> v2->v3:
> - Split up rzv2h_dedicated_pins into common and pcie1 subsets to
>   facilitate reuse for RZ/V2N.

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-pinctrl for v6.16.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ