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Message-ID: <20250502132005.611698-4-tanmay@marvell.com>
Date: Fri, 2 May 2025 18:49:44 +0530
From: Tanmay Jagdale <tanmay@...vell.com>
To: <bbrezillon@...nel.org>, <arno@...isbad.org>, <schalla@...vell.com>,
<herbert@...dor.apana.org.au>, <davem@...emloft.net>,
<sgoutham@...vell.com>, <lcherian@...vell.com>, <gakula@...vell.com>,
<jerinj@...vell.com>, <hkelam@...vell.com>, <sbhatta@...vell.com>,
<andrew+netdev@...n.ch>, <edumazet@...gle.com>, <kuba@...nel.org>,
<pabeni@...hat.com>, <bbhushan2@...vell.com>, <bhelgaas@...gle.com>,
<pstanner@...hat.com>, <gregkh@...uxfoundation.org>,
<peterz@...radead.org>, <linux@...blig.org>,
<krzysztof.kozlowski@...aro.org>, <giovanni.cabiddu@...el.com>
CC: <linux-crypto@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<netdev@...r.kernel.org>, <rkannoth@...vell.com>, <sumang@...vell.com>,
<gcherian@...vell.com>, Tanmay Jagdale <tanmay@...vell.com>
Subject: [net-next PATCH v1 03/15] octeontx2-af: Setup Large Memory Transaction for crypto
From: Bharat Bhushan <bbhushan2@...vell.com>
Large Memory Transaction store (LMTST) operation is required
for enqueuing workto CPT hardware. An LMTST operation makes
one or more 128-byte write operation to normal, cacheable
memory region. This patch setup LMTST memory region for
enqueuing work to CPT hardware.
Signed-off-by: Bharat Bhushan <bbhushan2@...vell.com>
Signed-off-by: Tanmay Jagdale <tanmay@...vell.com>
---
.../net/ethernet/marvell/octeontx2/af/rvu.c | 1 +
.../net/ethernet/marvell/octeontx2/af/rvu.h | 7 +++
.../ethernet/marvell/octeontx2/af/rvu_cpt.c | 51 +++++++++++++++++++
.../ethernet/marvell/octeontx2/af/rvu_cpt.h | 4 ++
4 files changed, 63 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index d9f000cda5e5..ea346e59835b 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -731,6 +731,7 @@ static void rvu_free_hw_resources(struct rvu *rvu)
rvu_npa_freemem(rvu);
rvu_npc_freemem(rvu);
rvu_nix_freemem(rvu);
+ rvu_cpt_freemem(rvu);
/* Free block LF bitmaps */
for (id = 0; id < BLK_COUNT; id++) {
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 6923fd756b19..6551fdb612dc 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -557,6 +557,12 @@ struct rvu_cpt {
struct rvu_cpt_inst_queue cpt0_iq;
struct rvu_cpt_inst_queue cpt1_iq;
struct rvu_cpt_rx_inline_lf_cfg rx_cfg;
+
+ /* CPT LMTST */
+ void *lmt_base;
+ u64 lmt_addr;
+ size_t lmt_size;
+ dma_addr_t lmt_iova;
};
struct rvu {
@@ -1086,6 +1092,7 @@ int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
int slot);
int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
int rvu_cpt_init(struct rvu *rvu);
+void rvu_cpt_freemem(struct rvu *rvu);
#define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
#define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
index 89e0739ba414..8ed56ac512ef 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
@@ -1874,10 +1874,46 @@ int rvu_mbox_handler_cpt_rx_inline_lf_cfg(struct rvu *rvu,
#define MAX_RXC_ICB_CNT GENMASK_ULL(40, 32)
+static int rvu_cpt_lmt_init(struct rvu *rvu)
+{
+ struct lmtst_tbl_setup_req req;
+ dma_addr_t iova;
+ void *base;
+ int size;
+ int err;
+
+ if (is_rvu_otx2(rvu))
+ return 0;
+
+ memset(&req, 0, sizeof(struct lmtst_tbl_setup_req));
+
+ size = LMT_LINE_SIZE * LMT_BURST_SIZE + OTX2_ALIGN;
+ base = dma_alloc_attrs(rvu->dev, size, &iova, GFP_ATOMIC,
+ DMA_ATTR_FORCE_CONTIGUOUS);
+ if (!base)
+ return -ENOMEM;
+
+ req.lmt_iova = ALIGN(iova, OTX2_ALIGN);
+ req.use_local_lmt_region = true;
+ err = rvu_mbox_handler_lmtst_tbl_setup(rvu, &req, NULL);
+ if (err) {
+ dma_free_attrs(rvu->dev, size, base, iova,
+ DMA_ATTR_FORCE_CONTIGUOUS);
+ return err;
+ }
+
+ rvu->rvu_cpt.lmt_addr = (__force u64)PTR_ALIGN(base, OTX2_ALIGN);
+ rvu->rvu_cpt.lmt_base = base;
+ rvu->rvu_cpt.lmt_size = size;
+ rvu->rvu_cpt.lmt_iova = iova;
+ return 0;
+}
+
int rvu_cpt_init(struct rvu *rvu)
{
struct rvu_hwinfo *hw = rvu->hw;
u64 reg_val;
+ int ret;
/* Retrieve CPT PF number */
rvu->cpt_pf_num = get_cpt_pf_num(rvu);
@@ -1898,6 +1934,21 @@ int rvu_cpt_init(struct rvu *rvu)
spin_lock_init(&rvu->cpt_intr_lock);
+ ret = rvu_cpt_lmt_init(rvu);
+ if (ret)
+ return ret;
+
mutex_init(&rvu->rvu_cpt.lock);
return 0;
}
+
+void rvu_cpt_freemem(struct rvu *rvu)
+{
+ if (is_rvu_otx2(rvu))
+ return;
+
+ if (rvu->rvu_cpt.lmt_base)
+ dma_free_attrs(rvu->dev, rvu->rvu_cpt.lmt_size,
+ rvu->rvu_cpt.lmt_base, rvu->rvu_cpt.lmt_iova,
+ DMA_ATTR_FORCE_CONTIGUOUS);
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.h
index 4b57c7038d6c..e6fa247a03ba 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.h
@@ -49,6 +49,10 @@
#define OTX2_CPT_INLINE_RX_OPCODE (0x26 | (1 << 6))
#define CN10K_CPT_INLINE_RX_OPCODE (0x29 | (1 << 6))
+/* CPT LMTST */
+#define LMT_LINE_SIZE 128 /* LMT line size in bytes */
+#define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst */
+
/* Calculate CPT register offset */
#define CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \
(((blk) << 20) | ((slot) << 12) | (offs))
--
2.43.0
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