linux-kernel - Re: [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board

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Message-ID: <frlw5n2fxu5wxrlaahiuwlgaeg4rsqk7ushpcgvc2q4mzorrzf@e4axknhir4el>
Date: Fri, 2 May 2025 17:45:03 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: george.moussalem@...look.com
Cc: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, Luo Jie <quic_luoj@...cinc.com>,
        Lee Jones <lee@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use
 fixed factor clock

On Fri, May 02, 2025 at 02:15:48PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@...look.com>
> 
> The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output
> clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4
> to the analog block routing channel.
> 
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts             | 3 ++-
>  arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++-
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi                      | 3 ++-
>  3 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> index 8460b538eb6a3e2d6b971bd9637309809e0c0f0c..abb629678c023a2eb387ebf229f6dd1c30133b19 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> @@ -80,5 +80,6 @@ &usbphy0 {
>  };
>  
>  &xo_board_clk {
> -	clock-frequency = <24000000>;
> +	clock-div = <4>;
> +	clock-mult = <1>;
>  };
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
> index 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a185437886b04b0d99e8e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
> @@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
>  };
>  
>  &xo_board_clk {
> -	clock-frequency = <24000000>;
> +	clock-div = <4>;
> +	clock-mult = <1>;
>  };

Is the divider a part of the SoC? If so, please move these values to the SoC dtsi file.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 78368600ba44825b38f737a6d7837a80dc32efb6..7e40f80e4795de25d55b5a19c1beb98e5abcdef3 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -31,7 +31,8 @@ sleep_clk: sleep-clk {
>  		};
>  
>  		xo_board_clk: xo-board-clk {
> -			compatible = "fixed-clock";
> +			compatible = "fixed-factor-clock";
> +			clocks = <&ref_96mhz_clk>;
>  			#clock-cells = <0>;
>  		};
>  
> 
> -- 
> 2.49.0
> 
> 

-- 
With best wishes
Dmitry