linux-kernel - [PATCH v3 04/13] dt-bindings: x86: Add CPU bindings for x86

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Message-Id: <20250503191515.24041-5-ricardo.neri-calderon@linux.intel.com>
Date: Sat,  3 May 2025 12:15:06 -0700
From: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
To: x86@...nel.org,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Rob Herring <robh@...nel.org>,
	"K. Y. Srinivasan" <kys@...rosoft.com>,
	Haiyang Zhang <haiyangz@...rosoft.com>,
	Wei Liu <wei.liu@...nel.org>,
	Dexuan Cui <decui@...rosoft.com>,
	Michael Kelley <mhklinux@...look.com>
Cc: devicetree@...r.kernel.org,
	Saurabh Sengar <ssengar@...ux.microsoft.com>,
	Chris Oo <cho@...rosoft.com>,
	linux-hyperv@...r.kernel.org,
	"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
	linux-acpi@...r.kernel.org ,
	linux-kernel@...r.kernel.org,
	"Ravi V. Shankar" <ravi.v.shankar@...el.com>,
	Ricardo Neri <ricardo.neri@...el.com>
Subject: [PATCH v3 04/13] dt-bindings: x86: Add CPU bindings for x86

Add bindings for CPUs in x86 architecture. Start by defining the `reg` and
`enable-method` properties and their relationship to x86 APIC ID and the
available mechanisms to boot secondary CPUs.

Start defining bindings for Intel processors. Bindings for other vendors
can be added later as needed.

Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
---
 .../devicetree/bindings/x86/cpus.yaml         | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/x86/cpus.yaml

diff --git a/Documentation/devicetree/bindings/x86/cpus.yaml b/Documentation/devicetree/bindings/x86/cpus.yaml
new file mode 100644
index 000000000000..108b3ad64aea
--- /dev/null
+++ b/Documentation/devicetree/bindings/x86/cpus.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/x86/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: x86 CPUs
+
+maintainers:
+  - Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
+
+description: |
+  Description of x86 CPUs in a system through the "cpus" node.
+
+  Detailed information about the CPU architecture can be found in the Intel
+  Software Developer's Manual:
+    https://intel.com/sdm
+
+properties:
+  compatible:
+    enum:
+      - intel,x86
+
+  reg:
+    description: |
+      Local APIC ID of the CPU. If the CPU has more than one execution thread,
+      then the property is an array with one element per thread.
+
+  enable-method:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: |
+      The method used to wake up secondary CPUs. This property is not needed if
+      the secondary processors are booted using INIT assert, de-assert followed
+      by Start-Up IPI messages as described in the Volume 3, Section 11.4 of
+      Intel Software Developer's Manual.
+
+      It is also optional for the bootstrap CPU.
+
+    oneOf:
+      - items:
+          - const: intel,wakeup-mailbox
+            description: |
+              CPUs are woken up using the mailbox mechanism. The platform
+              firmware boots the secondary CPUs and puts them in a state
+              to check the mailbox for a wakeup command from the operating
+              system.
+
+required:
+  - reg
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    /*
+     * A system with two CPUs. cpu@0 is the bootstrap CPU and its status is
+     * "okay". It does not have the enable-method property. cpu@1 is a
+     * secondary CPU. Its status is "disabled" and defines the enable-method
+     * property.
+     */
+
+    cpus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      cpu@0 {
+        reg = <0x0 0x1>;
+        compatible = "intel,x86";
+        status = "okay";
+      };
+
+      cpu@1 {
+        reg = <0x0 0x1>;
+        compatible = "intel,x86";
+        status = "disabled";
+        enable-method = "intel,wakeup-mailbox";
+      };
+    };
+
-- 
2.43.0