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Message-Id: <20250505221419.2672473-450-sashal@kernel.org> Date: Mon, 5 May 2025 18:11:06 -0400 From: Sasha Levin <sashal@...nel.org> To: linux-kernel@...r.kernel.org, stable@...r.kernel.org Cc: Damon Ding <damon.ding@...k-chips.com>, Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, Vinod Koul <vkoul@...nel.org>, Sasha Levin <sashal@...nel.org>, kishon@...nel.org, heiko@...ech.de, linux-phy@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org Subject: [PATCH AUTOSEL 6.14 450/642] phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REF From: Damon Ding <damon.ding@...k-chips.com> [ Upstream commit 2947c8065e9efdd3b6434d2817dc8896234a3fc0 ] According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097) to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0 selects the ROPLL. Signed-off-by: Damon Ding <damon.ding@...k-chips.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org> Link: https://lore.kernel.org/r/20250205105157.580060-2-damon.ding@rock-chips.com Signed-off-by: Vinod Koul <vkoul@...nel.org> Signed-off-by: Sasha Levin <sashal@...nel.org> --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 2fb4f297fda3d..920abf6fa9bdd 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -94,8 +94,8 @@ #define LCPLL_ALONE_MODE BIT(1) /* CMN_REG(0097) */ #define DIG_CLK_SEL BIT(1) -#define ROPLL_REF BIT(1) -#define LCPLL_REF 0 +#define LCPLL_REF BIT(1) +#define ROPLL_REF 0 /* CMN_REG(0099) */ #define CMN_ROPLL_ALONE_MODE BIT(2) #define ROPLL_ALONE_MODE BIT(2) -- 2.39.5
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