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Message-ID: <20250506003811.92405-2-riel@surriel.com>
Date: Mon, 5 May 2025 20:37:39 -0400
From: Rik van Riel <riel@...riel.com>
To: linux-kernel@...r.kernel.org
Cc: linux-mm@...ck.org,
x86@...nel.org,
kernel-team@...a.com,
dave.hansen@...ux.intel.com,
luto@...nel.org,
peterz@...radead.org,
tglx@...utronix.de,
mingo@...hat.com,
bp@...en8.de,
hpa@...or.com,
Yu-cheng Yu <yu-cheng.yu@...el.com>,
Rik van Riel <riel@...riel.com>
Subject: [RFC PATCH 1/9] x86/mm: Introduce MSR_IA32_CORE_CAPABILITIES
From: Yu-cheng Yu <yu-cheng.yu@...el.com>
MSR_IA32_CORE_CAPABILITIES indicates the existence of other MSRs.
Bit[1] indicates Remote Action Request (RAR) TLB registers.
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@...el.com>
Signed-off-by: Rik van Riel <riel@...riel.com>
---
arch/x86/include/asm/msr-index.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ac21dc19dde2..0828b891fe2e 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -212,6 +212,12 @@
* File.
*/
+#define MSR_IA32_CORE_CAPABILITIES 0x000000cf
+#define CORE_CAP_RAR BIT(1) /*
+ * Remote Action Request. Used to directly
+ * flush the TLB on remote CPUs.
+ */
+
#define MSR_IA32_FLUSH_CMD 0x0000010b
#define L1D_FLUSH BIT(0) /*
* Writeback and invalidate the
--
2.49.0
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