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Message-ID: <20250506050437.10264-18-darwi@linutronix.de>
Date: Tue, 6 May 2025 07:04:28 +0200
From: "Ahmed S. Darwish" <darwi@...utronix.de>
To: Ingo Molnar <mingo@...hat.com>,
Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Andrew Cooper <andrew.cooper3@...rix.com>,
"H. Peter Anvin" <hpa@...or.com>,
John Ogness <john.ogness@...utronix.de>,
x86@...nel.org,
x86-cpuid@...ts.linux.dev,
LKML <linux-kernel@...r.kernel.org>,
"Ahmed S. Darwish" <darwi@...utronix.de>
Subject: [PATCH v1 17/26] x86/cpuid: Remove direct CPUID(0x2) query API
All call sites at x86/cpu and x86/cacheinfo has been switched from direct
CPUID(0x2) access to scanned CPUID access. Remove the direct CPUID(0x2)
query APIs at <asm/cpuid/leaf_0x2_api.h>.
Rename the iterator macro:
for_each_scanned_leaf_0x2_entry()
back to:
for_each_leaf_0x2_entry()
since the "for_each_scanned_.." name and was just chosen to accommodate
the direct CPUID(0x2) to scanned CPUID(0x2) transition.
Signed-off-by: Ahmed S. Darwish <darwi@...utronix.de>
---
arch/x86/include/asm/cpuid/leaf_0x2_api.h | 72 +----------------------
arch/x86/kernel/cpu/cacheinfo.c | 2 +-
arch/x86/kernel/cpu/intel.c | 2 +-
3 files changed, 5 insertions(+), 71 deletions(-)
diff --git a/arch/x86/include/asm/cpuid/leaf_0x2_api.h b/arch/x86/include/asm/cpuid/leaf_0x2_api.h
index be3d7e113421..98876bcb38c3 100644
--- a/arch/x86/include/asm/cpuid/leaf_0x2_api.h
+++ b/arch/x86/include/asm/cpuid/leaf_0x2_api.h
@@ -2,76 +2,10 @@
#ifndef _ASM_X86_CPUID_LEAF_0x2_API_H
#define _ASM_X86_CPUID_LEAF_0x2_API_H
-#include <asm/cpuid/api.h>
#include <asm/cpuid/types.h>
-/**
- * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
- * @regs: Output parameter
- *
- * Query CPUID leaf 0x2 and store its output in @regs. Force set any
- * invalid 1-byte descriptor returned by the hardware to zero (the NULL
- * cache/TLB descriptor) before returning it to the caller.
- *
- * Use for_each_leaf_0x2_entry() to iterate over the register output in
- * parsed form.
- */
-static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
-{
- cpuid_leaf(0x2, regs);
-
- /*
- * All Intel CPUs must report an iteration count of 1. In case
- * of bogus hardware, treat all returned descriptors as NULL.
- */
- if (regs->desc[0] != 0x01) {
- for (int i = 0; i < 4; i++)
- regs->regv[i] = 0;
- return;
- }
-
- /*
- * The most significant bit (MSB) of each register must be clear.
- * If a register is invalid, replace its descriptors with NULL.
- */
- for (int i = 0; i < 4; i++) {
- if (regs->reg[i].invalid)
- regs->regv[i] = 0;
- }
-}
-
/**
* for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
- * @regs: Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
- * @__ptr: u8 pointer, for macro internal use only
- * @entry: Pointer to parsed descriptor information at each iteration
- *
- * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
- * @regs. Provide the parsed information for each descriptor through @entry.
- *
- * To handle cache-specific descriptors, switch on @entry->c_type. For TLB
- * descriptors, switch on @entry->t_type.
- *
- * Example usage for cache descriptors::
- *
- * const struct leaf_0x2_table *entry;
- * union leaf_0x2_regs regs;
- * u8 *ptr;
- *
- * cpuid_get_leaf_0x2_regs(®s);
- * for_each_leaf_0x2_entry(regs, ptr, entry) {
- * switch (entry->c_type) {
- * ...
- * }
- * }
- */
-#define for_each_leaf_0x2_entry(regs, __ptr, entry) \
- for (__ptr = &(regs).desc[1]; \
- __ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]); \
- __ptr++)
-
-/**
- * for_each_scanned_leaf_0x2_entry() - Iterator for parsed CPUID(0x2) descriptors
* @regs: Leaf 0x2 register output, as returned by cpudata_cpuid_regs()
* @__ptr: u8 pointer, for macro internal use only
* @entry: Pointer to parsed descriptor information at each iteration
@@ -99,9 +33,9 @@ static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
* }
* }
*/
-#define for_each_scanned_leaf_0x2_entry(regs, __ptr, entry) \
- for (({ static_assert(sizeof(*regs) == sizeof(union leaf_0x2_regs)); }), \
- __ptr = &((union leaf_0x2_regs *)(regs))->desc[1]; \
+#define for_each_leaf_0x2_entry(regs, __ptr, entry) \
+ for (({ static_assert(sizeof(*regs) == sizeof(union leaf_0x2_regs)); }), \
+ __ptr = &((union leaf_0x2_regs *)(regs))->desc[1]; \
__ptr < &((union leaf_0x2_regs *)(regs))->desc[16] && (entry = &cpuid_0x2_table[*__ptr]);\
__ptr++)
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 696ef5e9e14b..665f3b187964 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -389,7 +389,7 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
if (!regs)
return;
- for_each_scanned_leaf_0x2_entry(regs, ptr, entry) {
+ for_each_leaf_0x2_entry(regs, ptr, entry) {
switch (entry->c_type) {
case CACHE_L1_INST: l1i += entry->c_size; break;
case CACHE_L1_DATA: l1d += entry->c_size; break;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 24b506a28ce8..5cefe726c18d 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -717,7 +717,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
if (!regs)
return;
- for_each_scanned_leaf_0x2_entry(regs, ptr, entry)
+ for_each_leaf_0x2_entry(regs, ptr, entry)
intel_tlb_lookup(entry);
}
--
2.49.0
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