linux-kernel - Re: [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer

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Message-ID: <20250506-bonehead-security-fdd71309a721@spud>
Date: Tue, 6 May 2025 17:27:39 +0100
From: Conor Dooley <conor@...nel.org>
To: Ben Zong-You Xie <ben717@...estech.com>
Cc: devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org, paul.walmsley@...ive.com,
	palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr,
	robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
	tglx@...utronix.de, daniel.lezcano@...aro.org,
	prabhakar.mahadev-lad.rj@...renesas.com, tim609@...estech.com
Subject: Re: [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer

On Sat, May 03, 2025 at 11:18:25PM +0800, Ben Zong-You Xie wrote:
> Add the DT binding documentation for Andes machine timer.
> 
> The RISC-V architecture defines a machine timer that provides a real-time
> counter and generates timer interrupts. Andes machiner timer (PLMT0) is
> the implementation of the machine timer, and it contains memory-mapped
> registers (mtime and mtimecmp). This device supports up to 32 cores.
> 
> Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

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