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Message-ID: <aBo92LQh4WYXyRXK@gmail.com>
Date: Tue, 6 May 2025 18:50:32 +0200
From: Ingo Molnar <mingo@...nel.org>
To: Ard Biesheuvel <ardb+git@...gle.com>
Cc: linux-kernel@...r.kernel.org, x86@...nel.org,
Ard Biesheuvel <ardb@...nel.org>,
Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [RFC PATCH 3/3] x86/boot: Use alternatives based selector for
5-level paging constants
* Ard Biesheuvel <ardb+git@...gle.com> wrote:
> +static inline int __attribute_const__ choose_l5_enabled(int yes, int no)
> +{
> + int ret = no;
> +
> + asm_inline(ALTERNATIVE_TERNARY("jmp 6f; 8:", %c[feat], "movl %[yes], %[ret]", "")
> + " .pushsection .altinstr_aux,\"ax\" \n"
> + "6: pushfq \n"
> + " testb $1, %a[l5en] \n"
> + " jz 7f \n"
> + " movl %[yes], %[ret] \n"
> + "7: popfq \n"
> + " jmp 8b \n"
> + " .popsection \n"
> + : [ret] "+rm" (ret)
> + : [feat] "i" (X86_FEATURE_LA57),
> + [yes] "i" (yes),
> + [l5en] "i" (&__pgtable_l5_enabled));
> +
> + return ret;
So why not create a new synthethic cpufeature flag,
X86_FEATURE_LA57_ENABLED or so, which could then be queried via the
regular facilities? This ternary logic is not really needed, because
the hardware isn't ternary. :)
With that we could do with only a single, obvious line of ALTERNATIVE()
assembly:
#define ALTERNATIVES_CONST_U32(__val1, __val2, __feature) \
({ \
u32 __val; \
\
asm_inline (ALTERNATIVE("movl $" #__val1 ", %0", "movl $" __val2 ", %0", __feature) :"=g" (__val)); \
\
__val; \
})
...
#define MAX_PHYSMEM_BITS ALTERNATIVE_CONST_U32(46, 52, X86_FEATURE_LA57_ENABLED)
Thanks,
Ingo
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