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Message-ID: <174657514016.201370.7208767895794181355.b4-ty@gmail.com>
Date: Wed,  7 May 2025 07:45:54 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Chen Wang <unicorn_wang@...look.com>,
	Richard Cochran <richardcochran@...il.com>,
	Vinod Koul <vkoul@...nel.org>,
	Alexander Sverdlin <alexander.sverdlin@...il.com>,
	Nikita Shubin <nikita.shubin@...uefel.me>,
	Linus Walleij <linus.walleij@...aro.org>,
	Arnd Bergmann <arnd@...db.de>,
	Inochi Amaoto <inochiama@...il.com>
Cc: linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org,
	sophgo@...ts.linux.dev,
	linux-kernel@...r.kernel.org,
	netdev@...r.kernel.org,
	Yixun Lan <dlan@...too.org>,
	Longbin Li <looong.bin@...il.com>
Subject: Re: (subset) [PATCH v5 0/5] clk: sophgo: add SG2044 clock controller support

On Fri, 18 Apr 2025 10:03:19 +0800, Inochi Amaoto wrote:
> The clock controller of SG2044 provides multiple clocks for various
> IPs on the SoC, including PLL, mux, div and gates. As the PLL and
> div have obvious changed and do not fit the framework of SG2042,
> a new implement is provided to handle these.
> 
> Changed from v4:
> 1. patch 1,3: Applied Krzysztof's tag.
> 2. patch 1: fix header path in description.
> 3. patch 4: drop duplicated module alias.
> 4. patch 5: make sg2044_clk_desc_data const.
> 
> [...]

Applied to sophgo-clk-for-6.16-rc1, thanks!

[1/5] dt-bindings: soc: sophgo: Add SG2044 top syscon device
      https://github.com/sophgo/linux/commit/e4b700d38957526fbcec6d7bb5890ad4c1192241
[3/5] dt-bindings: clock: sophgo: add clock controller for SG2044
      https://github.com/sophgo/linux/commit/1a215904986e48ce04ac8f24ecb5b18cb6beaf43
[4/5] clk: sophgo: Add PLL clock controller support for SG2044 SoC
      https://github.com/sophgo/linux/commit/ff5240793b0484187a836f6e1b7f0e376e0776ed

Thanks,
Inochi


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