linux-kernel - [PATCH AUTOSEL 6.6 175/294] clocksource: mips-gic-timer: Enable counter when CPUs start

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Message-Id: <20250505225634.2688578-175-sashal@kernel.org>
Date: Mon,  5 May 2025 18:54:35 -0400
From: Sasha Levin <sashal@...nel.org>
To: linux-kernel@...r.kernel.org,
	stable@...r.kernel.org
Cc: Paul Burton <paulburton@...nel.org>,
	Chao-ying Fu <cfu@...ecomp.com>,
	Dragan Mladjenovic <dragan.mladjenovic@...mia.com>,
	Aleksandar Rikalo <arikalo@...il.com>,
	Philippe Mathieu-Daudé <philmd@...aro.org>,
	Serge Semin <fancer.lancer@...il.com>,
	Gregory CLEMENT <gregory.clement@...tlin.com>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
	Sasha Levin <sashal@...nel.org>,
	tglx@...utronix.de,
	linux-mips@...r.kernel.org
Subject: [PATCH AUTOSEL 6.6 175/294] clocksource: mips-gic-timer: Enable counter when CPUs start

From: Paul Burton <paulburton@...nel.org>

[ Upstream commit 3128b0a2e0cf6e07aa78e5f8cf7dd9cd59dc8174 ]

In multi-cluster MIPS I6500 systems there is a GIC in each cluster,
each with its own counter. When a cluster powers up the counter will
be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register.

In single cluster systems, it has been fine to clear COUNTSTOP once
in gic_clocksource_of_init() to start the counter. In multi-cluster
systems, this will only have started the counter in the boot cluster,
and any CPUs in other clusters will find their counter stopped which
will break the GIC clock_event_device.

Resolve this by having CPUs clear the COUNTSTOP bit when they come
online, using the existing gic_starting_cpu() CPU hotplug callback. This
will allow CPUs in secondary clusters to ensure that the cluster's GIC
counter is running as expected.

Signed-off-by: Paul Burton <paulburton@...nel.org>
Signed-off-by: Chao-ying Fu <cfu@...ecomp.com>
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@...mia.com>
Signed-off-by: Aleksandar Rikalo <arikalo@...il.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@...aro.org>
Tested-by: Serge Semin <fancer.lancer@...il.com>
Tested-by: Gregory CLEMENT <gregory.clement@...tlin.com>
Acked-by: Daniel Lezcano <daniel.lezcano@...aro.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 drivers/clocksource/mips-gic-timer.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index b3ae38f367205..39c70b5ac44c9 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -114,6 +114,9 @@ static void gic_update_frequency(void *data)
 
 static int gic_starting_cpu(unsigned int cpu)
 {
+	/* Ensure the GIC counter is running */
+	clear_gic_config(GIC_CONFIG_COUNTSTOP);
+
 	gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
 	return 0;
 }
@@ -248,9 +251,6 @@ static int __init gic_clocksource_of_init(struct device_node *node)
 			pr_warn("Unable to register clock notifier\n");
 	}
 
-	/* And finally start the counter */
-	clear_gic_config(GIC_CONFIG_COUNTSTOP);
-
 	/*
 	 * It's safe to use the MIPS GIC timer as a sched clock source only if
 	 * its ticks are stable, which is true on either the platforms with
-- 
2.39.5