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Message-ID: <4e00a764-23df-4bd9-85d3-f32cb153a9b6@kwiboo.se>
Date: Tue, 6 May 2025 01:12:21 +0200
From: Jonas Karlman <jonas@...boo.se>
To: Chukun Pan <amadeus@....edu.cn>, Heiko Stuebner <heiko@...ech.de>
Cc: Yao Zi <ziyao@...root.org>, Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v3 1/2] arm64: dts: rockchip: Add pwm nodes for RK3528
On 2025-04-01 14:00, Chukun Pan wrote:
> Add pwm nodes for RK3528. The PWM core on RK3528 is the same as
> RK3328, but the driver does not support interrupts yet.
>
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>
pwm0-pwm2 has been verified working on my rk3528 boards and remaining
seem to be correct, I have also dropped my prior attempt of looking into
multi-channel handling as mentioned in v2, so this is:
Reviewed-by: Jonas Karlman <jonas@...boo.se>
Regards,
Jonas
> ---
> arch/arm64/boot/dts/rockchip/rk3528.dtsi | 80 ++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> index 35704d0be37a..47d4f63f11d3 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -465,6 +465,86 @@ uart7: serial@...28000 {
> status = "disabled";
> };
>
> + pwm0: pwm@...90000 {
> + compatible = "rockchip,rk3528-pwm",
> + "rockchip,rk3328-pwm";
> + reg = <0x0 0xffa90000 0x0 0x10>;
> + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
> + clock-names = "pwm", "pclk";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1: pwm@...90010 {
> + compatible = "rockchip,rk3528-pwm",
> + "rockchip,rk3328-pwm";
> + reg = <0x0 0xffa90010 0x0 0x10>;
> + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
> + clock-names = "pwm", "pclk";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2: pwm@...90020 {
> + compatible = "rockchip,rk3528-pwm",
> + "rockchip,rk3328-pwm";
> + reg = <0x0 0xffa90020 0x0 0x10>;
> + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
> + clock-names = "pwm", "pclk";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm3: pwm@...90030 {
> + compatible = "rockchip,rk3528-pwm",
> + "rockchip,rk3328-pwm";
> + reg = <0x0 0xffa90030 0x0 0x10>;
> + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
> + clock-names = "pwm", "pclk";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm4: pwm@...98000 {
> + compatible = "rockchip,rk3528-pwm",
> + "rockchip,rk3328-pwm";
> + reg = <0x0 0xffa98000 0x0 0x10>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
> + clock-names = "pwm", "pclk";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm5: pwm@...98010 {
> + compatible = "rockchip,rk3528-pwm",
> + "rockchip,rk3328-pwm";
> + reg = <0x0 0xffa98010 0x0 0x10>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
> + clock-names = "pwm", "pclk";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm6: pwm@...98020 {
> + compatible = "rockchip,rk3528-pwm",
> + "rockchip,rk3328-pwm";
> + reg = <0x0 0xffa98020 0x0 0x10>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
> + clock-names = "pwm", "pclk";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm7: pwm@...98030 {
> + compatible = "rockchip,rk3528-pwm",
> + "rockchip,rk3328-pwm";
> + reg = <0x0 0xffa98030 0x0 0x10>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
> + clock-names = "pwm", "pclk";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> saradc: adc@...e0000 {
> compatible = "rockchip,rk3528-saradc";
> reg = <0x0 0xffae0000 0x0 0x10000>;
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