linux-kernel - [PATCH AUTOSEL 5.10 056/114] fpga: altera-cvp: Increase credit timeout

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Message-Id: <20250505231817.2697367-56-sashal@kernel.org>
Date: Mon,  5 May 2025 19:17:19 -0400
From: Sasha Levin <sashal@...nel.org>
To: linux-kernel@...r.kernel.org,
	stable@...r.kernel.org
Cc: Kuhanh Murugasen Krishnan <kuhanh.murugasen.krishnan@...el.com>,
	Ang Tien Sung <tien.sung.ang@...el.com>,
	Xu Yilun <yilun.xu@...el.com>,
	Xu Yilun <yilun.xu@...ux.intel.com>,
	Sasha Levin <sashal@...nel.org>,
	mdf@...nel.org,
	hao.wu@...el.com,
	linux-fpga@...r.kernel.org
Subject: [PATCH AUTOSEL 5.10 056/114] fpga: altera-cvp: Increase credit timeout

From: Kuhanh Murugasen Krishnan <kuhanh.murugasen.krishnan@...el.com>

[ Upstream commit 0f05886a40fdc55016ba4d9ae0a9c41f8312f15b ]

Increase the timeout for SDM (Secure device manager) data credits from
20ms to 40ms. Internal stress tests running at 500 loops failed with the
current timeout of 20ms. At the start of a FPGA configuration, the CVP
host driver reads the transmit credits from SDM. It then sends bitstream
FPGA data to SDM based on the total credits. Each credit allows the
CVP host driver to send 4kBytes of data. There are situations whereby,
the SDM did not respond in time during testing.

Signed-off-by: Ang Tien Sung <tien.sung.ang@...el.com>
Signed-off-by: Kuhanh Murugasen Krishnan <kuhanh.murugasen.krishnan@...el.com>
Acked-by: Xu Yilun <yilun.xu@...el.com>
Link: https://lore.kernel.org/r/20250212221249.2715929-1-tien.sung.ang@intel.com
Signed-off-by: Xu Yilun <yilun.xu@...ux.intel.com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 drivers/fpga/altera-cvp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
index 4e0edb60bfba6..d107ad73a188c 100644
--- a/drivers/fpga/altera-cvp.c
+++ b/drivers/fpga/altera-cvp.c
@@ -52,7 +52,7 @@
 /* V2 Defines */
 #define VSE_CVP_TX_CREDITS		0x49	/* 8bit */
 
-#define V2_CREDIT_TIMEOUT_US		20000
+#define V2_CREDIT_TIMEOUT_US		40000
 #define V2_CHECK_CREDIT_US		10
 #define V2_POLL_TIMEOUT_US		1000000
 #define V2_USER_TIMEOUT_US		500000
-- 
2.39.5