linux-kernel - Re: [PATCH] ACPI/PPTT: fix off-by-one error

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Message-ID: <20250507-divergent-lori-from-pluto-71daee@sudeepholla>
Date: Wed, 7 May 2025 13:56:53 +0100
From: Sudeep Holla <sudeep.holla@....com>
To: "Heyne, Maximilian" <mheyne@...zon.de>
Cc: "stable@...r.kernel.org" <stable@...r.kernel.org>,
	Sudeep Holla <sudeep.holla@....com>,
	"Rafael J. Wysocki" <rafael@...nel.org>,
	Len Brown <lenb@...nel.org>, Ard Biesheuvel <ardb@...nel.org>,
	Jeremy Linton <jeremy.linton@....com>,
	Catalin Marinas <catalin.marinas@....com>,
	"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ACPI/PPTT: fix off-by-one error

On Wed, May 07, 2025 at 12:42:14PM +0000, Heyne, Maximilian wrote:
> On Wed, May 07, 2025 at 01:30:53PM +0100, Sudeep Holla wrote:
> > On Wed, May 07, 2025 at 11:56:48AM +0000, Heyne, Maximilian wrote:
> > > On Wed, May 07, 2025 at 12:52:18PM +0100, Sudeep Holla wrote:
> > > > 
> > > > Just to understand, this node is absolutely processor node with no
> > > > private resources ? I find it hard to trust this as most of the CPUs
> > > > do have L1 I&D caches. If they were present the table can't abruptly end
> > > > like this.
> > > 
> > > Yes looks like it. In our case the ACPI subtable has length 0x14 which is
> > > exactly sizeof(acpi_pptt_processor).
> > > 
> > 
> > OK, this seem like it is emulated platform with no private resources as
> > it is specified in the other similar patch clearly(QEMU/VM). So this
> > doesn't match real platforms. Your PPTT is wrong if it is real hardware
> > platform as you must have private resources.
> > 
> > Anyways if we allow emulation to present CPUs without private resources
> > we may have to consider allowing this as the computed pointer will match
> > the table end.
> 
> Is there a need by the ACPI specification that the Cache information
> must come after the processor information? Because on our platform there
> is Cache and it's described but at a different location seemingly. It
> looks like caches are described first and then the CPUs.
>

That is fine but you must have reference to those caches in the processor
node and the length of the node won't be 0x14 in that case and you shouldn't
hit this issue. So if this is real platform, then yes I am must say you
PPTT is wrong especially if there are caches in the table as you say just
that processor nodes are not pointing to them correctly then ?

> I can try to drill even deeper here if you insist. As said I'm no
> subject matter expert here. But is there something obviously wrong with
> my patch or would it be ok to just take it?
>

Yes you much check your PPTT if it is real hardware platform. I am OK
with the change in terms of QEMU or VM. You may need to reword commit
message a bit. I will respond separately.

-- 
Regards,
Sudeep