linux-kernel - Re: [PATCH net-next v7 8/8] mfd: zl3073x: Register DPLL sub-device during init

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAHp75Ven0i05QhKz2djYx0UU9E9nipb7Qw3mm4e+UN+ZSF_enA@mail.gmail.com>
Date: Wed, 7 May 2025 16:41:44 +0300
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Ivan Vecera <ivecera@...hat.com>
Cc: netdev@...r.kernel.org, Vadim Fedorenko <vadim.fedorenko@...ux.dev>, 
	Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>, Jiri Pirko <jiri@...nulli.us>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Prathosh Satish <Prathosh.Satish@...rochip.com>, "David S. Miller" <davem@...emloft.net>, 
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Simon Horman <horms@...nel.org>, 
	Lee Jones <lee@...nel.org>, Andy Shevchenko <andy@...nel.org>, Michal Schmidt <mschmidt@...hat.com>, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-doc@...r.kernel.org
Subject: Re: [PATCH net-next v7 8/8] mfd: zl3073x: Register DPLL sub-device
 during init

On Wed, May 7, 2025 at 3:45 PM Ivan Vecera <ivecera@...hat.com> wrote:
>
> Register DPLL sub-devices to expose the functionality provided
> by ZL3073x chip family. Each sub-device represents one of
> the available DPLL channels.

...

> +static const struct zl3073x_pdata zl3073x_pdata[ZL3073X_MAX_CHANNELS] = {
> +       { .channel = 0, },
> +       { .channel = 1, },
> +       { .channel = 2, },
> +       { .channel = 3, },
> +       { .channel = 4, },
> +};

> +static const struct mfd_cell zl3073x_devs[] = {
> +       ZL3073X_CELL("zl3073x-dpll", 0),
> +       ZL3073X_CELL("zl3073x-dpll", 1),
> +       ZL3073X_CELL("zl3073x-dpll", 2),
> +       ZL3073X_CELL("zl3073x-dpll", 3),
> +       ZL3073X_CELL("zl3073x-dpll", 4),
> +};

> +#define ZL3073X_MAX_CHANNELS   5

Btw, wouldn't be better to keep the above lists synchronised like

1. Make ZL3073X_CELL() to use indexed variant

[idx] = ...

2. Define the channel numbers

and use them in both data structures.

...

OTOH, I'm not sure why we even need this. If this is going to be
sequential, can't we make a core to decide which cell will be given
which id?

--
With Best Regards,
Andy Shevchenko