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Message-Id: <20250507031019.4080541-1-quic_ziyuzhan@quicinc.com>
Date: Wed, 7 May 2025 11:10:13 +0800
From: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
To: vkoul@...nel.org, kishon@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, dmitry.baryshkov@...aro.org,
neil.armstrong@...aro.org, abel.vesa@...aro.org,
manivannan.sadhasivam@...aro.org, lpieralisi@...nel.org, kw@...ux.com,
bhelgaas@...gle.com, andersson@...nel.org, konradybcio@...nel.org
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-pci@...r.kernel.org, quic_qianyu@...cinc.com,
quic_krichai@...cinc.com, quic_vbadigan@...cinc.com,
Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Subject: [PATCH v5 0/6] pci: qcom: Add QCS8300 PCIe support
This series adds document, phy, configs support for PCIe in QCS8300.
The series depend on the following devicetree.
This series depends on PCIe SMMU for QCS8300:
https://lore.kernel.org/all/dc535643-235d-46e9-b241-7d7b0e75e6ac@oss.qualcomm.com/
Have follwing changes:
- Add dedicated schema for the PCIe controllers found on QCS8300.
- Add compatible for qcs8300 platform.
- Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
- Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
---
Changes in v5:
- Add QCOM PCIe controller version in commit msg (Mani)
- Modify platform dts change subject (Dmitry)
- Update bindings to fix the dtb check errors.
- Remove qcs8300 compatible in driver, do not need it (Dmitry)
- Fixed compile error found by kernel test robot
- Link to v4: https://lore.kernel.org/linux-phy/20241220055239.2744024-1-quic_ziyuzhan@quicinc.com/
Changes in v4:
- Add received tag
- Fixed compile error found by kernel test robot
- Link to v3: https://lore.kernel.org/lkml/202412211301.bQO6vXpo-lkp@intel.com/T/#mdd63e5be39acbf879218aef91c87b12d4540e0f7
Changes in v3:
- Add received tag(Rob & Dmitry)
- Update pcie_phy in gcc node to soc dtsi(Dmitry & Konrad)
- remove pcieprot0 node(Konrad & Mani)
- Fix format comments(Konrad)
- Update base-commit to tag: next-20241213(Bjorn)
- Corrected of_device_id.data from 1.9.0 to 1.34.0.
- Link to v2: https://lore.kernel.org/all/20241128081056.1361739-1-quic_ziyuzhan@quicinc.com/
Changes in v2:
- Fix some format comments and match the style in x1e80100(Konrad)
- Add global interrupt for PCIe0 and PCIe1(Konrad)
- split the soc dtsi and the platform dts into two changes(Konrad)
- Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@quicinc.com/
Ziyue Zhang (6):
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
for sa8775p
dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300
arm64: dts: qcom: qcs8300: enable pcie0
arm64: dts: qcom: qcs8300-ride: enable pcie0 interface
arm64: dts: qcom: qcs8300: enable pcie1
arm64: dts: qcom: qcs8300-ride: enable pcie1 interface
.../bindings/pci/qcom,pcie-sa8775p.yaml | 26 +-
.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 4 +-
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 80 +++++
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 297 +++++++++++++++++-
4 files changed, 396 insertions(+), 11 deletions(-)
base-commit: a269b93a67d815c8215fbfadeb857ae5d5f519d3
--
2.34.1
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