linux-kernel - Re: [PATCH net-next v8 0/8] Add Microchip ZL3073x support (part 1)

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Message-ID: <2c41caf5-0579-42d8-8f7e-4a9b1a0baa48@redhat.com>
Date: Wed, 7 May 2025 18:13:11 +0200
From: Ivan Vecera <ivecera@...hat.com>
To: netdev@...r.kernel.org
Cc: Vadim Fedorenko <vadim.fedorenko@...ux.dev>,
 Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
 Jiri Pirko <jiri@...nulli.us>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Prathosh Satish <Prathosh.Satish@...rochip.com>,
 "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>,
 Paolo Abeni <pabeni@...hat.com>, Simon Horman <horms@...nel.org>,
 Lee Jones <lee@...nel.org>, Andy Shevchenko <andy@...nel.org>,
 Michal Schmidt <mschmidt@...hat.com>, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org
Subject: Re: [PATCH net-next v8 0/8] Add Microchip ZL3073x support (part 1)

On 07. 05. 25 5:24 odp., Ivan Vecera wrote:
> Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
> provides DPLL and PTP functionality. This series bring first part
> that adds the common MFD driver that provides an access to the bus
> that can be either I2C or SPI.
> 
> The next part of the series is bringing the DPLL driver that will
> covers DPLL functionality. Another series will bring PTP driver and
> flashing capability via devlink in the MFD driver will follow soon.
> 
> Testing was done by myself and by Prathosh Satish on Microchip EDS2
> development board with ZL30732 DPLL chip connected over I2C bus.
> 
> Patch breakdown
> ===============
> Patch 1 - Common DT schema for DPLL device and pin
> Patch 2 - DT bindings for microchip,zl3073* devices
> Patch 3 - Basic support for I2C, SPI and regmap configuration
> Patch 4 - Devlink device registration and info
> Patch 5 - Helpers for reading and writing register mailboxes
> Patch 6 - Fetch invariant register values used by DPLL/PTP sub-drivers
> Patch 7 - Clock ID generation for DPLL driver
> Patch 8 - Register/create DPLL device cells
> 
> ---
> v7->v8:
> * replaced zl3073x_pdata array ZL3073X_PDATA macro in patch 8
> v6->v7:
> * pass channel number using platform data instead of mfd_cell->id
> v5->v6:
> * fixed devlink info firmware version to be running instead of fixed
> * added documentation for devlink info versions
> v4->v5:
> * fixed DT patches description
> * dropped mailbox API
> * added type-safe register access functions
> * added an ability to protect multi-op accesses
> v3->v4:
> * fixed shortcomings in DT patches
> * completely reworked register access
> * removed a need to manage locking during mailbox accesses by callers
> * regcache switched to maple
> * dev_err_probe() in probe path
> * static mfd cells during sub-devices registration
> v1->v3:
> * dropped macros for generating register access functions
> * register access functions are provided in <linux/mfd/zl3073x_regs.h>
> * fixed DT descriptions and compatible wildcard usage
> * reworked regmap locking
>    - regmap uses implicit locking
>    - mailbox registers are additionally protected by extra mutex
> * fixed regmap virtual address range
> * added regmap rbtree cache (only for page selector now)
> * dropped patches for exporting strnchrnul and for supporting mfg file
>    this will be maybe added later
> 
> Ivan Vecera (8):
>    dt-bindings: dpll: Add DPLL device and pin
>    dt-bindings: dpll: Add support for Microchip Azurite chip family
>    mfd: Add Microchip ZL3073x support
>    mfd: zl3073x: Add support for devlink device info
>    mfd: zl3073x: Protect operations requiring multiple register accesses
>    mfd: zl3073x: Fetch invariants during probe
>    mfd: zl3073x: Add clock_id field
>    mfd: zl3073x: Register DPLL sub-device during init
> 
>   .../devicetree/bindings/dpll/dpll-device.yaml |  76 ++
>   .../devicetree/bindings/dpll/dpll-pin.yaml    |  45 +
>   .../bindings/dpll/microchip,zl30731.yaml      | 115 +++
>   Documentation/networking/devlink/index.rst    |   1 +
>   Documentation/networking/devlink/zl3073x.rst  |  37 +
>   MAINTAINERS                                   |  11 +
>   drivers/mfd/Kconfig                           |  32 +
>   drivers/mfd/Makefile                          |   5 +
>   drivers/mfd/zl3073x-core.c                    | 872 ++++++++++++++++++
>   drivers/mfd/zl3073x-i2c.c                     |  68 ++
>   drivers/mfd/zl3073x-regs.h                    |  54 ++
>   drivers/mfd/zl3073x-spi.c                     |  68 ++
>   drivers/mfd/zl3073x.h                         |  31 +
>   include/linux/mfd/zl3073x-regs.h              |  88 ++
>   include/linux/mfd/zl3073x.h                   | 202 ++++
>   15 files changed, 1705 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/dpll/dpll-device.yaml
>   create mode 100644 Documentation/devicetree/bindings/dpll/dpll-pin.yaml
>   create mode 100644 Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
>   create mode 100644 Documentation/networking/devlink/zl3073x.rst
>   create mode 100644 drivers/mfd/zl3073x-core.c
>   create mode 100644 drivers/mfd/zl3073x-i2c.c
>   create mode 100644 drivers/mfd/zl3073x-regs.h
>   create mode 100644 drivers/mfd/zl3073x-spi.c
>   create mode 100644 drivers/mfd/zl3073x.h
>   create mode 100644 include/linux/mfd/zl3073x-regs.h
>   create mode 100644 include/linux/mfd/zl3073x.h

I apologize for this quick update not respecting the 24 hour grace
period, I was not aware of such rule and otherwise I would not have been
able to send the v8 before Monday.

Ivan