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Message-ID: <20250507-obedient-copperhead-from-arcadia-4b052e@kuoka>
Date: Wed, 7 May 2025 07:09:03 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Cc: vkoul@...nel.org, kishon@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, dmitry.baryshkov@...aro.org,
neil.armstrong@...aro.org, abel.vesa@...aro.org, manivannan.sadhasivam@...aro.org,
lpieralisi@...nel.org, kw@...ux.com, bhelgaas@...gle.com, andersson@...nel.org,
konradybcio@...nel.org, linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
quic_qianyu@...cinc.com, quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v5 1/6] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy:
Update pcie phy bindings for sa8775p
On Wed, May 07, 2025 at 11:10:14AM GMT, Ziyue Zhang wrote:
> qcs8300 pcie1 phy use the same clocks as sa8775p, in the review comments
> of qcs8300 patches, gcc aux clock should be removed and replace it with
> phy_aux clock.So move "qcom,sa8775p-qmp-gen4x4-pcie-phy" compatible from
> 7 clocks' list to 6 clocks' list to solve the dtb check error.
>
> qcs8300 pcie phy only use 6 clocks, so move qcs8300 gen4x2 pcie phy
> compatible from 7 clocks' list to 6 clocks' list.
I don't understand any of this. You just submitted the bindings not so
far ago. Does this mean they were never tested?
What does it mean that gcc aux clock should be removed in the review
comments?
Best regards,
Krzysztof
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