| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250507071315.394857-25-herve.codina@bootlin.com>
Date: Wed, 7 May 2025 09:13:06 +0200
From: Herve Codina <herve.codina@...tlin.com>
To: Andrew Lunn <andrew@...n.ch>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Danilo Krummrich <dakr@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Andi Shyti <andi.shyti@...nel.org>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Peter Rosin <peda@...ntia.se>,
Derek Kiernan <derek.kiernan@....com>,
Dragan Cvetic <dragan.cvetic@....com>,
Arnd Bergmann <arnd@...db.de>,
Herve Codina <herve.codina@...tlin.com>,
Rob Herring <robh@...nel.org>,
Saravana Kannan <saravanak@...gle.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Mark Brown <broonie@...nel.org>,
Len Brown <lenb@...nel.org>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Daniel Scally <djrscally@...il.com>,
Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
Sakari Ailus <sakari.ailus@...ux.intel.com>
Cc: Wolfram Sang <wsa@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
linux-kernel@...r.kernel.org,
imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org,
linux-i2c@...r.kernel.org,
devicetree@...r.kernel.org,
linux-pci@...r.kernel.org,
linux-spi@...r.kernel.org,
linux-acpi@...r.kernel.org,
Allan Nielsen <allan.nielsen@...rochip.com>,
Horatiu Vultur <horatiu.vultur@...rochip.com>,
Steen Hegelund <steen.hegelund@...rochip.com>,
Luca Ceresoli <luca.ceresoli@...tlin.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: [PATCH v2 24/26] misc: lan966x_pci: Add dtsi/dtso nodes in order to support SFPs
Add device-tree nodes needed to support SFPs.
Those nodes are:
- the clock controller
- the i2c controller
- the i2c mux
- the SFPs themselves and their related ports in the switch
Signed-off-by: Herve Codina <herve.codina@...tlin.com>
---
drivers/misc/lan966x_evb_lan9662_nic.dtso | 95 +++++++++++++++++++++++
drivers/misc/lan966x_pci.dtsi | 42 ++++++++++
2 files changed, 137 insertions(+)
diff --git a/drivers/misc/lan966x_evb_lan9662_nic.dtso b/drivers/misc/lan966x_evb_lan9662_nic.dtso
index b3de5f14d9cb..20e1fe4f78bf 100644
--- a/drivers/misc/lan966x_evb_lan9662_nic.dtso
+++ b/drivers/misc/lan966x_evb_lan9662_nic.dtso
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/phy/phy-lan966x-serdes.h>
/dts-v1/;
@@ -28,15 +29,93 @@ __overlay__ {
#include "lan966x_pci.dtsi"
+ i2c0_emux: i2c0-emux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names = "i2c102", "i2c103", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_pins>;
+
+ i2c102: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c103: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ sfp2: sfp2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c102>;
+ tx-disable-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp3: sfp3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c103>;
+ tx-disable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
+ };
};
};
};
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&fc0_a_pins>;
+ pinctrl-names = "default";
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "okay";
+};
+
&gpio {
tod_pins: tod_pins {
pins = "GPIO_36";
function = "ptpsync_1";
};
+
+ fc0_a_pins: fcb4-i2c-pins {
+ /* RXD, TXD */
+ pins = "GPIO_9", "GPIO_10";
+ function = "fc0_a";
+ };
+
+ i2cmux_pins: i2cmux-pins {
+ pins = "GPIO_76", "GPIO_77";
+ function = "twi_slc_gate";
+ output-low;
+ };
+
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_76";
+ function = "twi_slc_gate";
+ output-high;
+ };
+
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_77";
+ function = "twi_slc_gate";
+ output-high;
+ };
};
&lan966x_phy0 {
@@ -65,6 +144,22 @@ &port1 {
status = "okay";
};
+&port2 {
+ phy-mode = "sgmii";
+ phys = <&serdes 2 SERDES6G(0)>;
+ sfp = <&sfp2>;
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&port3 {
+ phy-mode = "sgmii";
+ phys = <&serdes 3 SERDES6G(1)>;
+ sfp = <&sfp3>;
+ managed = "in-band-status";
+ status = "okay";
+};
+
&switch {
pinctrl-names = "default";
pinctrl-0 = <&tod_pins>;
diff --git a/drivers/misc/lan966x_pci.dtsi b/drivers/misc/lan966x_pci.dtsi
index 170298084fa5..d5c2056e4e5c 100644
--- a/drivers/misc/lan966x_pci.dtsi
+++ b/drivers/misc/lan966x_pci.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) 2025 Microchip UNG
*/
+#include <dt-bindings/clock/microchip,lan966x.h>
#include <dt-bindings/interrupt-controller/irq.h>
cpu_clk: clock-600000000 {
@@ -61,6 +62,39 @@ port1: port@1 {
reg = <1>;
status = "disabled";
};
+
+ port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+ };
+
+ flx0: flexcom@...40000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xe0040000 0x100>;
+ clocks = <&clks GCK_ID_FLEXCOM0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe0040000 0x800>;
+ status = "disabled";
+
+ i2c0: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupt-parent = <&oic>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clks GCK_ID_FLEXCOM0>;
+ assigned-clocks = <&clks GCK_ID_FLEXCOM0>;
+ assigned-clock-rates = <20000000>;
+ status = "disabled";
};
};
@@ -69,6 +103,14 @@ cpu_ctrl: syscon@...c0000 {
reg = <0xe00c0000 0xa8>;
};
+ clks: clock-controller@...c00a8 {
+ compatible = "microchip,lan966x-gck";
+ #clock-cells = <1>;
+ clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
+ clock-names = "cpu", "ddr", "sys";
+ reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
+ };
+
oic: oic@...c0120 {
compatible = "microchip,lan966x-oic";
#interrupt-cells = <2>;
--
2.49.0
Powered by blists - more mailing lists