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Message-ID: <CA+V-a8vokKwZOHTc5k4HCJVp0dfG=BSt53srA4KJtNEVi_3i2g@mail.gmail.com>
Date: Thu, 8 May 2025 16:47:53 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add GBETH nodes
Hi Geert,
Thank you for the review.
On Thu, May 8, 2025 at 4:01 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 28 Apr 2025 at 22:55, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Renesas RZ/V2H(P) SoC is equipped with 2x Synopsys DesignWare Ethernet
> > Quality-of-Service IP block version 5.20. Add GBETH nodes to R9A09G057
> > RZ/V2H(P) SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -701,6 +701,200 @@ sdhi2_vqmmc: vqmmc-regulator {
> > status = "disabled";
> > };
> > };
> > +
> > + eth0: ethernet@...30000 {
> > + compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth",
> > + "snps,dwmac-5.20";
> > + reg = <0 0x15c30000 0 0x10000>;
> > + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
>
> 775?
>
Ouch, I missed that.
> > + <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
> > + "rx-queue-0", "rx-queue-1", "rx-queue-2",
> > + "rx-queue-3", "tx-queue-0", "tx-queue-1",
> > + "tx-queue-2", "tx-queue-3";
> > + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
> > + <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>,
> > + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
> > + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
> > + clock-names = "stmmaceth", "pclk", "ptp_ref",
> > + "tx", "rx", "tx-180", "rx-180";
> > + resets = <&cpg 0xb0>;
>
> power-domains = <&cpg>;
>
Agreed.
> > + snps,multicast-filter-bins = <256>;
> > + snps,perfect-filter-entries = <128>;
> > + rx-fifo-depth = <8192>;
> > + tx-fifo-depth = <8192>;
> > + snps,fixed-burst;
> > + snps,no-pbl-x8;
> > + snps,force_thresh_dma_mode;
> > + snps,axi-config = <&stmmac_axi_setup>;
> > + snps,mtl-rx-config = <&mtl_rx_setup0>;
> > + snps,mtl-tx-config = <&mtl_tx_setup0>;
> > + snps,txpbl = <32>;
> > + snps,rxpbl = <32>;
> > + status = "disabled";
> > +
> > + mtl_rx_setup0: rx-queues-config {
> > + snps,rx-queues-to-use = <4>;
> > + snps,rx-sched-sp;
>
> Any specific reason the first instance has this property, while the
> second has not?
>
My initial intention was let the board DTS override it based on their
custom needs, but later thought maybe let's default something in the
SoC and later let the users update it based on the needs. I will add
this to both the nodes.
> > + eth1: ethernet@...40000 {
> > + compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth",
> > + "snps,dwmac-5.20";
> > + reg = <0 0x15c40000 0 0x10000>;
> > + interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
> > + "rx-queue-0", "rx-queue-1", "rx-queue-2",
> > + "rx-queue-3", "tx-queue-0", "tx-queue-1",
> > + "tx-queue-2", "tx-queue-3";
> > + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
> > + <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>,
> > + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
> > + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
> > + clock-names = "stmmaceth", "pclk", "ptp_ref",
> > + "tx", "rx", "tx-180", "rx-180";
> > + resets = <&cpg 0xb1>;
>
> power-domains = <&cpg>;
>
OK.
Cheers,
Prabhakar
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