Message-ID: <CAMuHMdVtQEEW3SU+f7qTDq6NVhy3LhrrwOgECdrZMfUk6vWQ2A@mail.gmail.com>
Date: Thu, 8 May 2025 18:05:48 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Richard Cochran <richardcochran@...il.com>, linux-renesas-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v3 1/2] clk: renesas: rzv2h-cpg: Skip monitor checks for
 external clocks

Hi Prabhakar,

On Mon, 28 Apr 2025 at 20:42, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Introduce support for module clocks that may be sourced from an external
> clock rather than the on-chip PLL. Add two new fields `external_clk` and
> `external_clk_mux_index` to `struct rzv2h_mod_clk` and `struct mod_clock`
> to mark such clocks and record the mux index corresponding to the external
> input.
>
> Provide a new helper macro `DEF_MOD_MUX_EXTERNAL()` for concise declaration
> of external-source module clocks.
>
> In `rzv2h_mod_clock_is_enabled()`, detect when the parent mux selects the
> external source (by comparing the current mux index against
> `external_clk_mux_index`) and skip the normal CLK_MON register check in
> that case. Update `rzv2h_cpg_register_mod_clk()` to populate the new fields
> from the SoC info.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v2->v3:
> - Renamed helper macro to `DEF_MOD_MUX_EXTERNAL()`.
> - Added a new field `external_clk_mux_index` to `struct mod_clock` to
>   store the mux index corresponding to the external input.
> - Updated the `rzv2h_mod_clock_is_enabled()` function to check if the
>   parent mux selects the external source by comparing the current mux
>   index against `external_clk_mux_index`.
> - Updated the `rzv2h_cpg_register_mod_clk()` function to populate the new
>   fields from the SoC info.
> - Updated commit description

Thanks for the update!

LGTM. But as I will not apply the second patch yet anyway, I am a
little bit more pedantic with my comments below (no offense intended,
though ;-)

> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -119,6 +119,8 @@ struct pll_clk {
>   * @on_bit: ON/MON bit
>   * @mon_index: monitor register offset
>   * @mon_bit: monitor bit
> + * @external_clk: Boolean flag indicating whether the parent clock can be an external clock
> + * @external_clk_mux_index: Index of the clock mux selection when the source is an external clock
>   */
>  struct mod_clock {
>         struct rzv2h_cpg_priv *priv;
> @@ -129,6 +131,8 @@ struct mod_clock {
>         u8 on_bit;
>         s8 mon_index;
>         u8 mon_bit;
> +       bool external_clk;
> +       u8 external_clk_mux_index;

Perhaps combine these two fields into

    s8 ext_clk_mux_index;

with -1 indicating not valid, cfr. mon_bit?


>  };
>
>  #define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
> @@ -567,10 +571,33 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
>  {
>         struct mod_clock *clock = to_mod_clock(hw);
>         struct rzv2h_cpg_priv *priv = clock->priv;
> +       bool skip_mon = false;
>         u32 bitmask;
>         u32 offset;
>
> -       if (clock->mon_index >= 0) {
> +       if (clock->mon_index >= 0 && clock->external_clk) {

I think the first condition can be dropped, as clock->external_clk
implies a valid mon_index.

> +               struct clk_hw *parent_hw;
> +               struct clk *parent_clk;
> +               struct clk_mux *mux;
> +               int index;
> +               u32 val;
> +
> +               parent_clk = clk_get_parent(hw->clk);
> +               if (IS_ERR(parent_clk))

Can this actually happen?

> +                       goto check_mon;
> +
> +               parent_hw = __clk_get_hw(parent_clk);
> +               mux = to_clk_mux(parent_hw);
> +
> +               val = readl(mux->reg) >> mux->shift;
> +               val &= mux->mask;
> +               index = clk_mux_val_to_index(parent_hw, mux->table, 0, val);
> +               if (index == clock->external_clk_mux_index)
> +                       skip_mon = true;
> +       }
> +
> +check_mon:
> +       if (clock->mon_index >= 0 && !skip_mon) {
>                 offset = GET_CLK_MON_OFFSET(clock->mon_index);
>                 bitmask = BIT(clock->mon_bit);
>

I am not so fond of the goto and the !skip_mon logic, and wonder
if we can improve? Perhaps spin of the index obtaining logic into a
parent_clk_mux_index() helper, and something like:

    int mon_index = clock->mon_index;

    if (clock->external_clk) {
            if (parent_clk_mux_index(hw) == clock->external_clk_mux_index))
                    mon_index = -1;
    }

    if (mon_index >= 0) {
            // do it
    }

> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -192,6 +192,8 @@ enum clk_types {
>   * @on_bit: ON bit
>   * @mon_index: monitor register index
>   * @mon_bit: monitor bit
> + * @external_clk: Boolean flag indicating whether the parent clock can be an external clock
> + * @external_clk_mux_index: Index of the clock mux selection when the source is an external clock
>   */
>  struct rzv2h_mod_clk {
>         const char *name;
> @@ -203,9 +205,12 @@ struct rzv2h_mod_clk {
>         u8 on_bit;
>         s8 mon_index;
>         u8 mon_bit;
> +       bool external_clk;
> +       u8 external_clk_mux_index;

s8 ext_clk_mux_index

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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