linux-kernel - Re: [PATCH v2] drm/etnaviv: Fix flush sequence logic

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Message-ID: <a18f214ab0487a1c562f9e2f7f66ab1345925177.camel@pengutronix.de>
Date: Thu, 08 May 2025 19:08:04 +0200
From: Lucas Stach <l.stach@...gutronix.de>
To: Tomeu Vizoso <tomeu@...euvizoso.net>, linux-kernel@...r.kernel.org
Cc: Russell King <linux+etnaviv@...linux.org.uk>, Christian Gmeiner
 <christian.gmeiner@...il.com>, David Airlie <airlied@...il.com>, Simona
 Vetter <simona@...ll.ch>, Philipp Zabel <p.zabel@...gutronix.de>, Guido
 Günther <agx@...xcpu.org>,
 etnaviv@...ts.freedesktop.org,  dri-devel@...ts.freedesktop.org
Subject: Re: [PATCH v2] drm/etnaviv: Fix flush sequence logic

Am Donnerstag, dem 08.05.2025 um 16:56 +0200 schrieb Tomeu Vizoso:
> We should be comparing the last submitted sequence number with that of
> the address space we may be switching to.
> 
This isn't the relevant change here though: if we switch the address
space, the comparison is moot, as we do a full flush on AS switch
anyway. The relevant change is that with the old code we would record
the flush sequence of the AS we switch away from as the current flush
sequence, so we might miss a necessary flush on the next submission if
that one doesn't require a AS switch, but would only flush based on
sequence mismatch.

Mind if I rewrite the commit message along those lines while applying?

Regards,
Lucas

> Fixes: 27b67278e007 ("drm/etnaviv: rework MMU handling")
> Signed-off-by: Tomeu Vizoso <tomeu@...euvizoso.net>
> ---
>  drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
> index b13a17276d07..88385dc3b30d 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
> @@ -347,7 +347,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
>  	u32 link_target, link_dwords;
>  	bool switch_context = gpu->exec_state != exec_state;
>  	bool switch_mmu_context = gpu->mmu_context != mmu_context;
> -	unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
> +	unsigned int new_flush_seq = READ_ONCE(mmu_context->flush_seq);
>  	bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;
>  	bool has_blt = !!(gpu->identity.minor_features5 &
>  			  chipMinorFeatures5_BLT_ENGINE);