linux-kernel - Re: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config

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Message-ID: <CAF6AEGtcoMZ+WiW5_BA4NFpLZsoOrDbkY4xyvENGoS2FQVwQxw@mail.gmail.com>
Date: Thu, 8 May 2025 11:41:12 -0700
From: Rob Clark <robdclark@...il.com>
To: Konrad Dybcio <konradybcio@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>, Abhinav Kumar <quic_abhinavk@...cinc.com>, 
	Dmitry Baryshkov <lumag@...nel.org>, Akhil P Oommen <quic_akhilpo@...cinc.com>, Sean Paul <sean@...rly.run>, 
	David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, 
	Marijn Suijten <marijn.suijten@...ainline.org>, linux-kernel@...r.kernel.org, 
	linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org, 
	freedreno@...ts.freedesktop.org, 
	Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config

On Thu, May 8, 2025 at 11:13 AM Konrad Dybcio <konradybcio@...nel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>
> Start the great despaghettification by getting a pointer to the common
> UBWC configuration, which houses e.g. UBWC versions that we need to
> make decisions.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 16 ++++++++++++++--
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c |  6 ++++++
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  3 +++
>  3 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
>         gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
>  }
>
> -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>  {
> +       /* Inherit the common config and make some necessary fixups */
> +       gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();

This does look a bit funny given the devm_kzalloc() below.. I guess
just so that the ptr is never NULL?

BR,
-R

> +       if (IS_ERR(gpu->common_ubwc_cfg))
> +               return -EINVAL;
> +
>         gpu->ubwc_config.rgb565_predicator = 0;
>         gpu->ubwc_config.uavflagprd_inv = 0;
>         gpu->ubwc_config.min_acc_len = 0;
> @@ -663,6 +668,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>                 gpu->ubwc_config.highest_bank_bit = 1;
>                 gpu->ubwc_config.min_acc_len = 1;
>         }
> +
> +       return 0;
>  }
>
>  static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> @@ -2540,7 +2547,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>                 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
>                                 a6xx_fault_handler);
>
> -       a6xx_calc_ubwc_config(adreno_gpu);
> +       ret = a6xx_calc_ubwc_config(adreno_gpu);
> +       if (ret) {
> +               a6xx_destroy(&(a6xx_gpu->base.base));
> +               return ERR_PTR(ret);
> +       }
> +
>         /* Set up the preemption specific bits and pieces for each ringbuffer */
>         a6xx_preempt_init(gpu);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 2348ffb35f7eb73a26da47881901d9111dca1ad9..b7f7eb8dcb272394dce8ed1e68310a394c1734a9 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -1149,6 +1149,12 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>                 speedbin = 0xffff;
>         adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>
> +       adreno_gpu->common_ubwc_cfg = devm_kzalloc(dev,
> +                                                  sizeof(*adreno_gpu->common_ubwc_cfg),
> +                                                  GFP_KERNEL);
> +       if (!adreno_gpu->common_ubwc_cfg)
> +               return -ENOMEM;
> +
>         gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
>                         ADRENO_CHIPID_ARGS(config->chip_id));
>         if (!gpu_name)
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index a8f4bf416e64fadbd1c61c991db13d539581e324..06be95d3efaee94e4107a484ad3132e0a6a9ea46 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -12,6 +12,8 @@
>  #include <linux/firmware.h>
>  #include <linux/iopoll.h>
>
> +#include <linux/soc/qcom/ubwc.h>
> +
>  #include "msm_gpu.h"
>
>  #include "adreno_common.xml.h"
> @@ -243,6 +245,7 @@ struct adreno_gpu {
>                  */
>                 u32 macrotile_mode;
>         } ubwc_config;
> +       const struct qcom_ubwc_cfg_data *common_ubwc_cfg;
>
>         /*
>          * Register offsets are different between some GPUs.
>
> --
> 2.49.0
>