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Message-ID: <9d20434f-f808-42a3-9282-d13c0a6f7fc5@quicinc.com>
Date: Thu, 8 May 2025 13:53:20 -0700
From: Jessica Zhang <quic_jesszhan@...cinc.com>
To: Jun Nie <jun.nie@...aro.org>, Rob Clark <robdclark@...il.com>,
"Abhinav
Kumar" <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>,
"Marijn
Suijten" <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst
<maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
Dmitry Baryshkov <lumag@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v9 11/14] drm/msm/dpu: blend pipes per mixer pairs config
On 5/6/2025 8:47 AM, Jun Nie wrote:
> Currently, only 2 pipes are used at most for a plane. A stage structure
> describes the configuration for a mixer pair. So only one stage is needed
> for current usage cases. The quad-pipe case will be added in future and 2
> stages are used in the case. So extend the stage to an array with array
> size STAGES_PER_PLANE and blend pipes per mixer pair with configuration in
> the stage structure.
>
> Signed-off-by: Jun Nie <jun.nie@...aro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@...cinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 45 +++++++++++++++++++----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +-
> 2 files changed, 31 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index d710b4eec7ad946a4cf74d6ac5f4db90e8dcf1fd..f35cb1f7a7d2c2c63b4228bc47b85bb57cddbe6b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -392,7 +392,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
> static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
> struct drm_plane *plane,
> struct dpu_crtc_mixer *mixer,
> - u32 num_mixers,
> + u32 lms_in_pair,
> enum dpu_stage stage,
> const struct msm_format *format,
> uint64_t modifier,
> @@ -426,7 +426,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
> stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index;
>
> /* blend config update */
> - for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
> + for (lm_idx = 0; lm_idx < lms_in_pair; lm_idx++)
> mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx);
> }
>
> @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> const struct msm_format *format;
> struct dpu_hw_ctl *ctl = mixer->lm_ctl;
>
> - uint32_t lm_idx, i;
> + uint32_t lm_idx, stage, i, pipe_idx, head_pipe_in_stage, lms_in_pair;
> bool bg_alpha_enable = false;
> DECLARE_BITMAP(fetch_active, SSPP_MAX);
>
> @@ -463,15 +463,24 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
> bg_alpha_enable = true;
>
> - for (i = 0; i < PIPES_PER_PLANE; i++) {
> - if (!pstate->pipe[i].sspp)
> - continue;
> - set_bit(pstate->pipe[i].sspp->idx, fetch_active);
> - _dpu_crtc_blend_setup_pipe(crtc, plane,
> - mixer, cstate->num_mixers,
> - pstate->stage,
> - format, fb ? fb->modifier : 0,
> - &pstate->pipe[i], i, stage_cfg);
> + /* loop pipe per mixer pair with config in stage structure */
> + for (stage = 0; stage < STAGES_PER_PLANE; stage++) {
> + head_pipe_in_stage = stage * PIPES_PER_STAGE;
> + for (i = 0; i < PIPES_PER_STAGE; i++) {
> + pipe_idx = i + head_pipe_in_stage;
> + if (!pstate->pipe[pipe_idx].sspp)
> + continue;
> + lms_in_pair = min(cstate->num_mixers - (stage * PIPES_PER_STAGE),
> + PIPES_PER_STAGE);
> + set_bit(pstate->pipe[pipe_idx].sspp->idx, fetch_active);
> + _dpu_crtc_blend_setup_pipe(crtc, plane,
> + &mixer[head_pipe_in_stage],
> + lms_in_pair,
> + pstate->stage,
> + format, fb ? fb->modifier : 0,
> + &pstate->pipe[pipe_idx], i,
> + &stage_cfg[stage]);
> + }
> }
>
> /* blend config update */
> @@ -503,7 +512,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
> struct dpu_crtc_mixer *mixer = cstate->mixers;
> struct dpu_hw_ctl *ctl;
> struct dpu_hw_mixer *lm;
> - struct dpu_hw_stage_cfg stage_cfg;
> + struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE];
> int i;
>
> DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
> @@ -516,9 +525,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
> }
>
> /* initialize stage cfg */
> - memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
> + memset(&stage_cfg, 0, sizeof(stage_cfg));
>
> - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
> + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, stage_cfg);
>
> for (i = 0; i < cstate->num_mixers; i++) {
> ctl = mixer[i].lm_ctl;
> @@ -535,8 +544,12 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
> mixer[i].mixer_op_mode,
> ctl->idx - CTL_0);
>
> + /*
> + * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg.
> + * stage data is shared between PIPES_PER_STAGE pipes.
> + */
> ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
> - &stage_cfg);
> + &stage_cfg[i / PIPES_PER_STAGE]);
> }
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index b0ed41108a32158c0bc3be2e25fc229b218fd6c5..7c74221380b2c05225c9f82ed6d33765042aec78 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -34,8 +34,9 @@
> #define DPU_MAX_PLANES 4
> #endif
>
> -#define PIPES_PER_PLANE 2
> +#define STAGES_PER_PLANE 1
> #define PIPES_PER_STAGE 2
> +#define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE)
> #ifndef DPU_MAX_DE_CURVES
> #define DPU_MAX_DE_CURVES 3
> #endif
>
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