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Message-ID: <20250508061012-GYB505240@gentoo>
Date: Thu, 8 May 2025 06:10:12 +0000
From: Yixun Lan <dlan@...too.org>
To: Haylen Chu <heylenay@....org>
Cc: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Haylen Chu <heylenay@...look.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
spacemit@...ts.linux.dev, Inochi Amaoto <inochiama@...look.com>,
Chen Wang <unicornxdotw@...mail.com>,
Jisheng Zhang <jszhang@...nel.org>,
Meng Zhang <zhangmeng.kevin@...ux.spacemit.com>,
Alex Elder <elder@...cstar.com>
Subject: Re: [PATCH v8 5/6] riscv: dts: spacemit: Add clock tree for SpacemiT
K1
Hi Haylen,
On 05:49 Thu 08 May , Haylen Chu wrote:
> Hi Yixun,
>
> On Wed, Apr 16, 2025 at 01:54:05PM +0000, Haylen Chu wrote:
> > Describe the PLL and system controllers that're capable of generating
> > clock signals in the devicetree.
> >
> > Signed-off-by: Haylen Chu <heylenay@....org>
> > Reviewed-by: Alex Elder <elder@...cstar.com>
> > Reviewed-by: Yixun Lan <dlan@...too.org>
> > ---
> > arch/riscv/boot/dts/spacemit/k1.dtsi | 75 ++++++++++++++++++++++++++++
> > 1 file changed, 75 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > index c670ebf8fa12..584f0dbc60f5 100644
> > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
>
> I found that I forgot to make the nodenames of syscons consistent:
> both "system-control" and "system-controller" are used, and pll should
> be named as "clock-controller" instead.
>
> Could you please drop the SoC devicetree patch then I could rework on
> it and correct the mistake?
Sure, I can drop previous DT patch, and re-apply, thanks
> Or I could follow up a clean up patch if
> dropping isn't easy or doesn't follow the convention.
>
> Thanks for your work,
> Haylen Chu
>
> > @@ -314,6 +346,17 @@ soc {
> > dma-noncoherent;
> > ranges;
> >
> > + syscon_apbc: system-control@...15000 {
> > + compatible = "spacemit,k1-syscon-apbc";
> > + reg = <0x0 0xd4015000 0x0 0x1000>;
> > + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> > + <&vctcxo_24m>;
> > + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> > + "vctcxo_24m";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > uart0: serial@...17000 {
> > compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > reg = <0x0 0xd4017000 0x0 0x100>;
> > @@ -409,6 +452,38 @@ pinctrl: pinctrl@...1e000 {
> > reg = <0x0 0xd401e000 0x0 0x400>;
> > };
> >
> > + syscon_mpmu: system-controller@...50000 {
> > + compatible = "spacemit,k1-syscon-mpmu";
> > + reg = <0x0 0xd4050000 0x0 0x209c>;
> > + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> > + <&vctcxo_24m>;
> > + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> > + "vctcxo_24m";
> > + #clock-cells = <1>;
> > + #power-domain-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + pll: system-control@...90000 {
> > + compatible = "spacemit,k1-pll";
> > + reg = <0x0 0xd4090000 0x0 0x1000>;
> > + clocks = <&vctcxo_24m>;
> > + spacemit,mpmu = <&syscon_mpmu>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + syscon_apmu: system-control@...82800 {
> > + compatible = "spacemit,k1-syscon-apmu";
> > + reg = <0x0 0xd4282800 0x0 0x400>;
> > + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> > + <&vctcxo_24m>;
> > + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> > + "vctcxo_24m";
> > + #clock-cells = <1>;
> > + #power-domain-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > plic: interrupt-controller@...00000 {
> > compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> > reg = <0x0 0xe0000000 0x0 0x4000000>;
> > --
> > 2.49.0
> >
--
Yixun Lan (dlan)
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