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Message-Id: <D9QOY9TMQXSX.2VOEKVRCXKOO1@ventanamicro.com>
Date: Thu, 08 May 2025 12:02:07 +0200
From: Radim Krčmář <rkrcmar@...tanamicro.com>
To: "Anup Patel" <anup@...infault.org>
Cc: <kvm-riscv@...ts.infradead.org>, <kvm@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, "Atish
Patra" <atishp@...shpatra.org>, "Paul Walmsley" <paul.walmsley@...ive.com>,
"Palmer Dabbelt" <palmer@...belt.com>, "Albert Ou" <aou@...s.berkeley.edu>,
"Alexandre Ghiti" <alex@...ti.fr>, "Andrew Jones"
<ajones@...tanamicro.com>, "Mayuresh Chitale" <mchitale@...tanamicro.com>
Subject: Re: [PATCH 3/5] KVM: RISC-V: remove unnecessary SBI reset state
2025-05-08T11:48:00+05:30, Anup Patel <anup@...infault.org>:
> On Thu, Apr 3, 2025 at 5:02 PM Radim Krčmář <rkrcmar@...tanamicro.com> wrote:
>>
>> The SBI reset state has only two variables -- pc and a1.
>> The rest is known, so keep only the necessary information.
>>
>> The reset structures make sense if we want userspace to control the
>> reset state (which we do), but I'd still remove them now and reintroduce
>> with the userspace interface later -- we could probably have just a
>> single reset state per VM, instead of a reset state for each VCPU.
>>
>> Signed-off-by: Radim Krčmář <rkrcmar@...tanamicro.com>
>
> Queued this patch for Linux-6.16
[5/5] was already applied, which means that [3/5] would be nicer with
memset(&vcpu->arch.smstateen_csr, 0, sizeof(vcpu->arch.smstateen_csr));
in the new function (kvm_riscv_vcpu_context_reset) where we memset(0)
the other csr context.
Should I add a patch to do that in v2?
Thanks.
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