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Message-ID: <63f0d0c0-94cc-4397-9c8a-b8d117514fd9@riscstar.com>
Date: Thu, 8 May 2025 06:37:31 -0500
From: Alex Elder <elder@...cstar.com>
To: Haylen Chu <heylenay@....org>, Michael Turquette
<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Haylen Chu <heylenay@...look.com>,
Yixun Lan <dlan@...too.org>, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>
Cc: linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
spacemit@...ts.linux.dev, Inochi Amaoto <inochiama@...look.com>,
Chen Wang <unicornxdotw@...mail.com>, Jisheng Zhang <jszhang@...nel.org>,
Meng Zhang <zhangmeng.kevin@...ux.spacemit.com>
Subject: Re: [PATCH v9] riscv: dts: spacemit: Add clock tree for SpacemiT K1
On 5/8/25 6:15 AM, Haylen Chu wrote:
> Describe the PLL and system controllers that're capable of generating
> clock signals in the devicetree.
>
> Signed-off-by: Haylen Chu <heylenay@....org>
> Reviewed-by: Alex Elder <elder@...cstar.com>
> Reviewed-by: Yixun Lan <dlan@...too.org>
> ---
>
> This originates the 5th patch from previous "Add clock controller
> support for SpacemiT K1" series[1] with node names of system
> controllers and PLL reworked[2].
>
> The patch is based on linux-spacemit/k1/clk-for-6.16. Yixun, please drop
> the previous version and pick this patch instead. Thanks for your work!
>
> [1]: https://lore.kernel.org/spacemit/20250416135406.16284-1-heylenay@4d2.org/
> [2]: https://lore.kernel.org/spacemit/aBxF81yqPgHP5oA_@ketchup/
What you changed was that previously you used "system-control" for
syscon_apbc, pll, and syscon_apmu. In this version, you name them
all "system-controller", consistently. Meanwhile syscon_mpmu had
"system-controller" already.
For example:
syscon_apbc: system-control@...15000 {
is now:
syscon_apbc: system-controller@...15000 {
This looks good to me. Thanks for updating it.
Reviewed-by: Alex Elder <elder@...cstar.com>
> arch/riscv/boot/dts/spacemit/k1.dtsi | 75 ++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index c670ebf8fa12..85c9730dd082 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -3,6 +3,8 @@
> * Copyright (C) 2024 Yangyu Chen <cyy@...self.name>
> */
>
> +#include <dt-bindings/clock/spacemit,k1-syscon.h>
> +
> /dts-v1/;
> / {
> #address-cells = <2>;
> @@ -306,6 +308,36 @@ cluster1_l2_cache: l2-cache1 {
> };
> };
>
> + clocks {
> + vctcxo_1m: clock-1m {
> + compatible = "fixed-clock";
> + clock-frequency = <1000000>;
> + clock-output-names = "vctcxo_1m";
> + #clock-cells = <0>;
> + };
> +
> + vctcxo_24m: clock-24m {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "vctcxo_24m";
> + #clock-cells = <0>;
> + };
> +
> + vctcxo_3m: clock-3m {
> + compatible = "fixed-clock";
> + clock-frequency = <3000000>;
> + clock-output-names = "vctcxo_3m";
> + #clock-cells = <0>;
> + };
> +
> + osc_32k: clock-32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + clock-output-names = "osc_32k";
> + #clock-cells = <0>;
> + };
> + };
> +
> soc {
> compatible = "simple-bus";
> interrupt-parent = <&plic>;
> @@ -314,6 +346,17 @@ soc {
> dma-noncoherent;
> ranges;
>
> + syscon_apbc: system-controller@...15000 {
> + compatible = "spacemit,k1-syscon-apbc";
> + reg = <0x0 0xd4015000 0x0 0x1000>;
> + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> + <&vctcxo_24m>;
> + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> + "vctcxo_24m";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> uart0: serial@...17000 {
> compatible = "spacemit,k1-uart", "intel,xscale-uart";
> reg = <0x0 0xd4017000 0x0 0x100>;
> @@ -409,6 +452,38 @@ pinctrl: pinctrl@...1e000 {
> reg = <0x0 0xd401e000 0x0 0x400>;
> };
>
> + syscon_mpmu: system-controller@...50000 {
> + compatible = "spacemit,k1-syscon-mpmu";
> + reg = <0x0 0xd4050000 0x0 0x209c>;
> + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> + <&vctcxo_24m>;
> + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> + "vctcxo_24m";
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + pll: clock-controller@...90000 {
> + compatible = "spacemit,k1-pll";
> + reg = <0x0 0xd4090000 0x0 0x1000>;
> + clocks = <&vctcxo_24m>;
> + spacemit,mpmu = <&syscon_mpmu>;
> + #clock-cells = <1>;
> + };
> +
> + syscon_apmu: system-controller@...82800 {
> + compatible = "spacemit,k1-syscon-apmu";
> + reg = <0x0 0xd4282800 0x0 0x400>;
> + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> + <&vctcxo_24m>;
> + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> + "vctcxo_24m";
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> plic: interrupt-controller@...00000 {
> compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> reg = <0x0 0xe0000000 0x0 0x4000000>;
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