linux-kernel - Re: [PATCH v4 3/5] arm64: dts: qcom: qcs615: enable pcie

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Message-ID: <96c54162-f985-46d9-820b-48868cfb1405@oss.qualcomm.com>
Date: Thu, 8 May 2025 16:47:23 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Ziyue Zhang <quic_ziyuzhan@...cinc.com>, vkoul@...nel.org,
        kishon@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, dmitry.baryshkov@...aro.org,
        neil.armstrong@...aro.org, abel.vesa@...aro.org,
        manivannan.sadhasivam@...aro.org, lpieralisi@...nel.org, kw@...ux.com,
        bhelgaas@...gle.com, andersson@...nel.org, konradybcio@...nel.org
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-pci@...r.kernel.org, quic_qianyu@...cinc.com,
        quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v4 3/5] arm64: dts: qcom: qcs615: enable pcie

On 5/7/25 5:15 AM, Ziyue Zhang wrote:
> From: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> 
> Add configurations in devicetree for PCIe0, including registers, clocks,
> interrupts and phy setting sequence.
> 
> Add PCIe lane equalization preset properties for 8 GT/s.
> 
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
> ---

[...]

> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
> +					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;

You added too many zeroes after &intc, this could not have worked

[...]

> +
> +			eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
> +					  0x5555 0x5555 0x5555 0x5555>;

very odd indentation, please put the 0x's under each other

Konrad