linux-kernel - Re: [PATCH v3 2/2] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1

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Message-ID: <CA+V-a8ukvn_K69h_COXS6JCqZbqXPQG1L9UAnm-gYQk7PTzb_g@mail.gmail.com>
Date: Fri, 9 May 2025 14:29:02 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Richard Cochran <richardcochran@...il.com>, linux-renesas-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v3 2/2] clk: renesas: r9a09g057: Add clock and reset
 entries for GBETH0/1

Hi Geert,

Thank you for the review.

On Thu, May 8, 2025 at 5:13 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 28 Apr 2025 at 20:42, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add clock and reset entries for GBETH instances. Include core clocks for
> > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > used as clock sources for the GBETH IP.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> > v2->v3:
> > - Used DEF_MOD_MUX_EXTERNAL() macro for external MUX clocks.
> > - Renamed gbe0/1 external mux clock names
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
> >         {0, 0},
> >  };
> >
> > +static const struct clk_div_table dtable_2_100[] = {
> > +       {0, 2},
> > +       {1, 10},
> > +       {2, 100},
> > +       {0, 0},
> > +};
> > +
> > +/* Mux clock tables */
> > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
> > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
> > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
> > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
> > +
> >  static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> >         /* External Clock Inputs */
> >         DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
>
> This patch starts to LGTM.  The only outstanding issue is how the
> et*_[rt]xclk will be provided.  I have read your comments on v2,
> and am eagerly awaiting the full patch set (CPG binding update, PHY
> updates, ...) to get this all to work.
>
My intention here is to get these initial patches in so that we have
Ethernet working on RZ/V2H (G3E/V2N) so that we have these boards on
LAVA and tackle et*_[rt]xclk clocks for the next cycle as this will
have to be discussed the -net maintainers. Are you OK with this
approach.

Cheers,
Prabhakar