linux-kernel - [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

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Message-ID: <20250509-dwindle-remold-98b3d03d0631@spud>
Date: Fri,  9 May 2025 16:37:57 +0100
From: Conor Dooley <conor@...nel.org>
To: linux-renesas-soc@...r.kernel.org
Cc: conor@...nel.org,
	Conor Dooley <conor.dooley@...rochip.com>,
	Ben Zong-You Xie <ben717@...estech.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org
Subject: [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp

From: Conor Dooley <conor.dooley@...rochip.com>

When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 .../devicetree/bindings/cache/andestech,ax45mp-cache.yaml      | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index d2cbe49f4e15f..f533bd178a9f6 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -28,6 +28,7 @@ select:
 properties:
   compatible:
     items:
+      - const: renesas,r9a07g043f-cache
       - const: andestech,ax45mp-cache
       - const: cache
 
@@ -70,7 +71,7 @@ examples:
     #include <dt-bindings/interrupt-controller/irq.h>
 
     cache-controller@...00000 {
-        compatible = "andestech,ax45mp-cache", "cache";
+        compatible = "renesas,r9a07g043f-cache", "andestech,ax45mp-cache", "cache";
         reg = <0x13400000 0x100000>;
         interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
         cache-line-size = <64>;
-- 
2.45.2