| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <aa852707-9be9-4e88-a0b3-034ebd47a9ac@gmail.com>
Date: Fri, 9 May 2025 19:29:40 +0300
From: Péter Ujfalusi <peter.ujfalusi@...il.com>
To: Sai Sree Kartheek Adivi <s-adivi@...com>, vkoul@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, nm@...com,
ssantosh@...nel.org, dmaengine@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
praneeth@...com, vigneshr@...com, u-kumar1@...com, a-chavda@...com
Subject: Re: [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci
On 28/04/2025 10:20, Sai Sree Kartheek Adivi wrote:
> Handle absence of tisci with direct register writes. This will support
> platforms that do not have tisci firmware like AM62L.
>
> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@...com>
> ---
> drivers/soc/ti/k3-ringacc.c | 162 +++++++++++++++++++++++++-----
> include/linux/soc/ti/k3-ringacc.h | 4 +
> 2 files changed, 142 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c
> index 82a15cad1c6c4..49e0483676a14 100644
> --- a/drivers/soc/ti/k3-ringacc.c
> +++ b/drivers/soc/ti/k3-ringacc.c
> @@ -45,6 +45,38 @@ struct k3_ring_rt_regs {
> u32 hwindx;
> };
>
> +#define K3_RINGACC_RT_CFG_REGS_OFS 0x40
> +#define K3_DMARING_CFG_ADDR_HI_MASK GENMASK(3, 0)
> +#define K3_DMARING_CFG_ASEL_SHIFT 16
> +#define K3_DMARING_CFG_SIZE_MASK GENMASK(15, 0)
> +
> +/**
> + * struct k3_ring_cfg_regs - The RA Configuration Registers region
> + *
> + * @ba_lo: Ring Base Address Low Register
> + * @ba_hi: Ring Base Address High Register
> + * @size: Ring Size Register
> + */
> +struct k3_ring_cfg_regs {
> + u32 ba_lo;
> + u32 ba_hi;
> + u32 size;
> +};
> +
> +#define K3_RINGACC_RT_INT_REGS_OFS 0x140
> +#define K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE BIT(0)
> +#define K3_RINGACC_RT_INT_ENABLE_SET_TR BIT(2)
> +
> +struct k3_ring_intr_regs {
> + u32 enable_set;
> + u32 resv_4;
> + u32 clr;
> + u32 resv_16;
> + u32 status_set;
> + u32 resv_8;
> + u32 status;
> +};
> +
> #define K3_RINGACC_RT_REGS_STEP 0x1000
> #define K3_DMARING_RT_REGS_STEP 0x2000
> #define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000
> @@ -157,6 +189,8 @@ struct k3_ring_state {
> */
> struct k3_ring {
> struct k3_ring_rt_regs __iomem *rt;
> + struct k3_ring_cfg_regs __iomem *cfg;
> + struct k3_ring_intr_regs __iomem *intr;
> struct k3_ring_fifo_regs __iomem *fifos;
> struct k3_ringacc_proxy_target_regs __iomem *proxy;
> dma_addr_t ring_mem_dma;
> @@ -465,16 +499,30 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring *ring)
> struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
> struct k3_ringacc *ringacc = ring->parent;
> int ret;
> + u32 reg;
>
> - ring_cfg.nav_id = ringacc->tisci_dev_id;
> - ring_cfg.index = ring->ring_id;
> - ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
> - ring_cfg.count = ring->size;
> + if (!ringacc->tisci) {
these are not in hot path, right?
The reg can be moved here and in other functions.
> + if (ring->cfg == NULL)
> + return;
> + reg = readl(&ring->cfg->size);
> + reg &= ~K3_DMARING_CFG_SIZE_MASK;
>
> - ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> - if (ret)
> - dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
> - ret, ring->ring_id);
> + writel(reg, &ring->cfg->size);
> + wmb();
> + reg |= ring->size;
> +
> + writel(reg, &ring->cfg->size);
> + } else {
> + ring_cfg.nav_id = ringacc->tisci_dev_id;
> + ring_cfg.index = ring->ring_id;
> + ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
> + ring_cfg.count = ring->size;
> +
> + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> + if (ret)
> + dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
> + ret, ring->ring_id);
> + }
> }
>
> void k3_ringacc_ring_reset(struct k3_ring *ring)
> @@ -494,16 +542,30 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring,
> struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
> struct k3_ringacc *ringacc = ring->parent;
> int ret;
> + u32 reg;
>
> ring_cfg.nav_id = ringacc->tisci_dev_id;
> ring_cfg.index = ring->ring_id;
> ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_MODE_VALID;
> ring_cfg.mode = mode;
>
> - ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> - if (ret)
> - dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
> - ret, ring->ring_id);
> + if (!ringacc->tisci) {
> + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
> + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
> + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
> + &ring->cfg->ba_hi);
> +
> + reg = readl(&ring->cfg->size);
> + reg &= ~K3_DMARING_CFG_SIZE_MASK;
> + reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
> +
> + writel(reg, &ring->cfg->size);
> + } else {
> + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> + if (ret)
> + dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
> + ret, ring->ring_id);
> + }
> }
>
> void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ)
> @@ -570,15 +632,29 @@ static void k3_ringacc_ring_free_sci(struct k3_ring *ring)
> struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
> struct k3_ringacc *ringacc = ring->parent;
> int ret;
> + u32 reg;
this can be added to if (!ringacc->tisci) { } scope.>
> ring_cfg.nav_id = ringacc->tisci_dev_id;
> ring_cfg.index = ring->ring_id;
> ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
>
> - ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> - if (ret)
> - dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
> - ret, ring->ring_id);
> + if (!ringacc->tisci) {
> + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
> + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
> + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
> + &ring->cfg->ba_hi);
> +
> + reg = readl(&ring->cfg->size);
> + reg &= ~K3_DMARING_CFG_SIZE_MASK;
> + reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
> +
> + writel(reg, &ring->cfg->size);
> + } else {
> + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> + if (ret)
> + dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
> + ret, ring->ring_id);
> + }
> }
>
> int k3_ringacc_ring_free(struct k3_ring *ring)
> @@ -669,15 +745,31 @@ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring)
> }
> EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num);
>
> +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring)
> +{
> + struct k3_ringacc *ringacc = ring->parent;
> + struct k3_ring *ring2 = &ringacc->rings[ring->ring_id];
> +
> + return readl(&ring2->intr->status);
> +}
> +EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_irq_status);
> +
> +void k3_ringacc_ring_clear_irq(struct k3_ring *ring)
> +{
> + struct k3_ringacc *ringacc = ring->parent;
> + struct k3_ring *ring2 = &ringacc->rings[ring->ring_id];
> +
> + writel(0xFF, &ring2->intr->status);
> +}
> +EXPORT_SYMBOL_GPL(k3_ringacc_ring_clear_irq);
> +
> static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
> {
> struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
> struct k3_ringacc *ringacc = ring->parent;
> + u32 reg;
> int ret;
>
> - if (!ringacc->tisci)
> - return -EINVAL;
> -
> ring_cfg.nav_id = ringacc->tisci_dev_id;
> ring_cfg.index = ring->ring_id;
> ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
> @@ -688,11 +780,26 @@ static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
> ring_cfg.size = ring->elm_size;
> ring_cfg.asel = ring->asel;
>
> + if (!ringacc->tisci) {
> + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo);
> + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) +
> + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT),
> + &ring->cfg->ba_hi);
> +
> + reg = readl(&ring->cfg->size);
> + reg &= ~K3_DMARING_CFG_SIZE_MASK;
> + reg |= ring_cfg.count & K3_DMARING_CFG_SIZE_MASK;
> +
> + writel(reg, &ring->cfg->size);
> + writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_SET_TR,
> + &ring->intr->enable_set);
> + return 0;
> + }
> +
> ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
> if (ret)
> dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
> - ret, ring->ring_id);
> -
> + ret, ring->ring_id);
suprious change? The alignment was correct.
> return ret;
> }
>
> @@ -1480,9 +1587,12 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
>
> mutex_init(&ringacc->req_lock);
>
> - base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
> - if (IS_ERR(base_rt))
> - return ERR_CAST(base_rt);
> + base_rt = data->base_rt;
> + if (!base_rt) {
> + base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
> + if (IS_ERR(base_rt))
> + return ERR_CAST(base_rt);
> + }
>
> ringacc->rings = devm_kzalloc(dev,
> sizeof(*ringacc->rings) *
> @@ -1498,6 +1608,10 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
> struct k3_ring *ring = &ringacc->rings[i];
>
> ring->rt = base_rt + K3_DMARING_RT_REGS_STEP * i;
> + ring->cfg = base_rt + K3_RINGACC_RT_CFG_REGS_OFS +
> + K3_DMARING_RT_REGS_STEP * i;
> + ring->intr = base_rt + K3_RINGACC_RT_INT_REGS_OFS +
> + K3_DMARING_RT_REGS_STEP * i;
> ring->parent = ringacc;
> ring->ring_id = i;
> ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
> diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ringacc.h
> index 39b022b925986..fcf6fbd4a8594 100644
> --- a/include/linux/soc/ti/k3-ringacc.h
> +++ b/include/linux/soc/ti/k3-ringacc.h
> @@ -158,6 +158,9 @@ u32 k3_ringacc_get_ring_id(struct k3_ring *ring);
> */
> int k3_ringacc_get_ring_irq_num(struct k3_ring *ring);
>
> +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring);
> +void k3_ringacc_ring_clear_irq(struct k3_ring *ring);
> +
> /**
> * k3_ringacc_ring_cfg - ring configure
> * @ring: pointer on ring
> @@ -262,6 +265,7 @@ struct k3_ringacc_init_data {
> const struct ti_sci_handle *tisci;
> u32 tisci_dev_id;
> u32 num_rings;
> + void __iomem *base_rt;
> };
>
> struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev,
--
Péter
Powered by blists - more mailing lists