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Message-ID: <aB29hOrv0nU73RCn@stanley.mountain>
Date: Fri, 9 May 2025 11:32:04 +0300
From: Dan Carpenter <dan.carpenter@...aro.org>
To: Patrice Chotard <patrice.chotard@...s.st.com>
Cc: Krzysztof Kozlowski <krzk@...nel.org>, Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, christophe.kerello@...s.st.com,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v11 2/3] memory: Add STM32 Octo Memory Manager driver
On Mon, Apr 28, 2025 at 10:58:31AM +0200, Patrice Chotard wrote:
> +static int stm32_omm_toggle_child_clock(struct device *dev, bool enable)
> +{
> + struct stm32_omm *omm = dev_get_drvdata(dev);
> + int i, ret;
> +
> + for (i = 0; i < omm->nb_child; i++) {
> + if (enable) {
> + ret = clk_prepare_enable(omm->clk_bulk[i + 1].clk);
> + if (ret) {
> + dev_err(dev, "Can not enable clock\n");
> + goto clk_error;
> + }
> + } else {
> + clk_disable_unprepare(omm->clk_bulk[i + 1].clk);
> + }
> + }
> +
> + return 0;
> +
> +clk_error:
> + while (i--)
> + clk_disable_unprepare(omm->clk_bulk[i + 1].clk);
> +
> + return ret;
> +}
> +
> +static int stm32_omm_disable_child(struct device *dev)
> +{
> + struct stm32_omm *omm = dev_get_drvdata(dev);
> + struct reset_control *reset;
> + int ret;
> + u8 i;
> +
> + ret = stm32_omm_toggle_child_clock(dev, true);
> + if (!ret)
^^^^
I'm pretty sure this was intended to be if (ret) and the ! is a typo.
> + return ret;
If it's not a typo please write this as:
if (!ret)
return 0;
regards,
dan carpenter
> +
> + for (i = 0; i < omm->nb_child; i++) {
> + /* reset OSPI to ensure CR_EN bit is set to 0 */
> + reset = omm->child_reset[i];
> + ret = reset_control_acquire(reset);
> + if (ret) {
> + stm32_omm_toggle_child_clock(dev, false);
> + dev_err(dev, "Can not acquire resset %d\n", ret);
> + return ret;
> + }
> +
> + reset_control_assert(reset);
> + udelay(2);
> + reset_control_deassert(reset);
> +
> + reset_control_release(reset);
> + }
> +
> + return stm32_omm_toggle_child_clock(dev, false);
> +}
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