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Message-Id: <20250509-james-nxp-spi-v1-8-32bfcd2fea11@linaro.org>
Date: Fri, 09 May 2025 12:05:55 +0100
From: James Clark <james.clark@...aro.org>
To: Vladimir Oltean <olteanv@...il.com>, Mark Brown <broonie@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Frank Li <Frank.Li@....com>,
Chester Lin <chester62515@...il.com>, Matthias Brugger <mbrugger@...e.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>,
NXP S32 Linux Team <s32@....com>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, larisa.grigore@....com, arnd@...aro.org,
andrei.stefanescu@....com, dan.carpenter@...aro.org
Cc: linux-spi@...r.kernel.org, imx@...ts.linux.dev,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Ciprian Marian Costea <ciprianmarian.costea@....com>,
James Clark <james.clark@...aro.org>
Subject: [PATCH 08/14] spi: spi-fsl-dspi: Use DMA for S32G controller in
target mode
From: Larisa Grigore <larisa.grigore@....com>
Switch to DMA for target mode otherwise the controller is too slow to
feed TX FIFO and UNDERFLOW occurs frequently. DMA can work only with 8
and 16 bits per word. 32bits per word is not supported, this is a
hardware limitation, so we keep the controller mode in TCFQ mode.
Signed-off-by: Larisa Grigore <larisa.grigore@....com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@....com>
Signed-off-by: James Clark <james.clark@...aro.org>
---
drivers/spi/spi-fsl-dspi.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index b7363cfc649d..50cec3b94322 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -137,7 +137,8 @@ enum {
LX2160A,
MCF5441X,
VF610,
- S32G
+ S32G,
+ S32G_TARGET
};
static const struct regmap_range dspi_yes_ranges[] = {
@@ -182,6 +183,7 @@ static const struct regmap_access_table dspi_volatile_table = {
enum {
DSPI_REGMAP,
+ S32G_DSPI_REGMAP,
DSPI_XSPI_REGMAP,
S32G_DSPI_XSPI_REGMAP,
DSPI_PUSHR
@@ -197,6 +199,15 @@ static const struct regmap_config dspi_regmap_config[] = {
.wr_table = &dspi_access_table,
.rd_table = &dspi_access_table
},
+ [S32G_DSPI_REGMAP] = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x8C,
+ .volatile_table = &dspi_volatile_table,
+ .wr_table = &s32g_dspi_access_table,
+ .rd_table = &s32g_dspi_access_table,
+ },
[DSPI_XSPI_REGMAP] = {
.reg_bits = 32,
.val_bits = 32,
@@ -294,6 +305,12 @@ static const struct fsl_dspi_devtype_data devtype_data[] = {
.max_clock_factor = 1,
.fifo_size = 5,
.regmap = &dspi_regmap_config[S32G_DSPI_XSPI_REGMAP]
+ },
+ [S32G_TARGET] = {
+ .trans_mode = DSPI_DMA_MODE,
+ .max_clock_factor = 1,
+ .fifo_size = 5,
+ .regmap = &dspi_regmap_config[S32G_DSPI_REGMAP]
}
};
@@ -350,6 +367,12 @@ struct fsl_dspi {
void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
};
+static bool is_s32g_dspi(struct fsl_dspi *data)
+{
+ return data->devtype_data == &devtype_data[S32G] ||
+ data->devtype_data == &devtype_data[S32G_TARGET];
+}
+
static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
{
switch (dspi->oper_word_size) {
@@ -1398,6 +1421,9 @@ static int dspi_probe(struct platform_device *pdev)
dspi->pushr_tx = 0;
}
+ if (spi_controller_is_target(ctlr) && is_s32g_dspi(dspi))
+ dspi->devtype_data = &devtype_data[S32G_TARGET];
+
if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
else
--
2.34.1
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