linux-kernel - Re: [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags

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Message-ID: <aB35aOZzdKZKMOht@arm.com>
Date: Fri, 9 May 2025 13:47:36 +0100
From: Catalin Marinas <catalin.marinas@....com>
To: Ankit Agrawal <ankita@...dia.com>
Cc: Jason Gunthorpe <jgg@...dia.com>, Oliver Upton <oliver.upton@...ux.dev>,
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Subject: Re: [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using
 VMA flags

On Wed, May 07, 2025 at 03:26:05PM +0000, Ankit Agrawal wrote:
> >> Unless FWB implies CTR_EL0.DIC (AFAIK, it doesn't) we may be
> >> restricting some CPUs.
> >
> > Yes, it will further narrow the CPUs down.
> > 
> > However, we just did this discussion for BBML2 + SMMUv3 SVA. I think
> > the same argument holds. If someone is crazy enough to build a CPU
> > with CXLish support and uses an old core without DIC, IDC and S2FWB
> > then they are going to have a bunch of work to fix the SW to support
> > it. Right now we know of no system that exists like this..
> >
> > Jason
> 
> Catalin, do you agree if I can go ahead and add the check for
> ARM64_HAS_CACHE_DIC?

As long as we don't leave out some hardware that has FWB but not DIC,
that's fine by me.

-- 
Catalin