linux-kernel - Re: [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

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Message-ID: <20250512-neglector-scope-65dd0e24db8f@spud>
Date: Mon, 12 May 2025 16:54:04 +0100
From: Conor Dooley <conor@...nel.org>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: linux-renesas-soc@...r.kernel.org,
	Conor Dooley <conor.dooley@...rochip.com>,
	Ben Zong-You Xie <ben717@...estech.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Magnus Damm <magnus.damm@...il.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache
 compatible

On Mon, May 12, 2025 at 03:57:41PM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
> 
> On Mon, 12 May 2025 at 15:48, Conor Dooley <conor@...nel.org> wrote:
> > From: Conor Dooley <conor.dooley@...rochip.com>
> >
> > When the binding was originally written, it was assumed that all
> > ax45mp-caches had the same properties etc. This has turned out to be
> > incorrect, as the QiLai SoC has a different number of cache-sets.
> >
> > Add a specific compatible for the RZ/Five for property enforcement and
> > in case there turns out to be additional differences between these
> > implementations of the cache controller.
> >
> > Acked-by: Ben Zong-You Xie <ben717@...estech.com>
> > Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> 
> Thanks for the update!
> 
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -143,7 +143,8 @@ plic: interrupt-controller@...00000 {
> >         };
> >
> >         l2cache: cache-controller@...00000 {
> > -               compatible = "andestech,ax45mp-cache", "cache";
> > +               compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> > +                            "cache";
> >                 reg = <0x0 0x13400000 0x0 0x100000>;
> >                 interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
> >                 cache-size = <0x40000>;
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> i.e. will queue in renesas-devel for v6.16 if there are no objections.

I'll grab the binding then on that basis. :+1:

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