linux-kernel - Re: [PATCH v1 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <aCFuqMM128wcjE0q@atctrx.andestech.com>
Date: Mon, 12 May 2025 11:44:40 +0800
From: Ben Zong-You Xie <ben717@...estech.com>
To: Conor Dooley <conor@...nel.org>
CC: <linux-renesas-soc@...r.kernel.org>,
        Conor Dooley
	<conor.dooley@...rochip.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof
 Kozlowski <krzk+dt@...nel.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Lad Prabhakar
	<prabhakar.mahadev-lad.rj@...renesas.com>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH v1 2/2] riscv: dts: renesas: add specific RZ/Five cache
 compatible

On Fri, May 09, 2025 at 04:37:59PM +0100, Conor Dooley wrote:
> [EXTERNAL MAIL]
> 
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
> 
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
> 
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>

Acked-by: Ben Zong-You Xie <ben717@...estech.com>