linux-kernel - Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

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Message-ID: <20250512193023.GA3708326-robh@kernel.org>
Date: Mon, 12 May 2025 14:30:23 -0500
From: Rob Herring <robh@...nel.org>
To: Vijay Balakrishna <vijayb@...ux.microsoft.com>
Cc: Borislav Petkov <bp@...en8.de>, Tony Luck <tony.luck@...el.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	James Morse <james.morse@....com>,
	Mauro Carvalho Chehab <mchehab@...nel.org>,
	Robert Richter <rric@...nel.org>, linux-edac@...r.kernel.org,
	linux-kernel@...r.kernel.org, Tyler Hicks <code@...icks.com>,
	Marc Zyngier <maz@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	devicetree@...r.kernel.org
Subject: Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

On Sun, May 04, 2025 at 05:27:40PM -0700, Vijay Balakrishna wrote:
> From: Sascha Hauer <s.hauer@...gutronix.de>
> 
> Some ARM Cortex CPUs like the A53, A57 and A72 have Error Detection And
> Correction (EDAC) support on their L1 and L2 caches. This is implemented
> in implementation defined registers, so usage of this functionality is
> not safe in virtualized environments or when EL3 already uses these
> registers. This patch adds a edac-enabled flag which can be explicitly
> set when EDAC can be used.
> 
> Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
> [vijayb: Added A72 to the commit message]
> Signed-off-by: Vijay Balakrishna <vijayb@...ux.microsoft.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index 2e666b2a4dcd..d1dc0a843d07 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -331,6 +331,12 @@ properties:
>        corresponding to the index of an SCMI performance domain provider, must be
>        "perf".
>  
> +  edac-enabled:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description:
> +      Some CPUs support Error Detection And Correction (EDAC) on their L1 and
> +      L2 caches. This flag marks this function as usable.
> +

Since we don't want this on newer cores, add an if/then schema to only 
allow this on A72 and whatever else you end up supporting.

Rob